Development of Topology and Modulation Method to Drive Indirect Matrix Converter Effectively NGUYEN DINH TUYEN i Development of Topology and Modulation Method to Drive Indirect Matrix Converter Effectively 2012 12 NGUYEN DINH TUYEN ii iii UNIVERSITY OF ULSAN Development of Topology and Modulation Method to Drive Indirect Matrix Converter Effectively by NGUYEN DINH TUYEN A thesis submitted in partial fulfillment for the degree of Doctor of Philosophy in the School of Electrical Engineering University of Ulsan iv v Abstract In recent years, the matrix converter (MC) has become more attractive because of the evolution of power device technologies and the development of large power integrated circuits. The MC is device used for converting directly from ac power to ac power without the intermediate energy storage component. The MC has some advantages such as high quality input/output current waveforms, controllable input power factor, operations in all four quadrants of the torque-speed and long life-time due to the absence of bulky electrolytic capacitors. Due to the provided significant advantages, it has been received extensive research attention for being alternative to replace traditional ac-dc-ac converters in real applications such as adjustable speed motor drive, renewable energy, power supply and many others.
The MC topologies are classified into two kinds: the direct matrix converter (DMC) and the indirect matrix converter (IMC). The IMC and DMC are similar in term of number of power switches and input/output current performance. In the last decade, the IMC has been received more attention than the DMC due to the IMC has some advantages that are not available in the DMC. This thesis concentrates on the development the modulation technique and topology of the IMC in order to control it effectively.
In this study, three new space vector modulation (SVM) methods are first proposed for IMC control. The modulation strategies are developed to reduce common-mode voltage. The comparison of three proposed modulation methods and the conventional method are carried out in term of: the peak value of common-mode voltage, the output voltage qualities and the possibility of voltage transfer ratio. The comparison results are confirmed both in the simulations and in the experimental tests.
vi In addition to developing new SVM methods for common-mode voltage reduction, this thesis establishes the carrier-based pulse width modulation (CBPWM) for the IMC. The SVM is flexible and widely used in industrial practice. However, it needs complex calculations and tables to synthesize the reference input current and the reference output voltage. A CBPWM scheme for the IMC is developed in order to overcome the drawbacks of the SVM method.
The advantage of the proposed algorithm is its ability use only one symmetrical triangular carrier signal to generate the gate signals for all of the power switches in both the rectifier and the inverter stages. The sinusoidal input and output currents, the maximum voltage transfer ratio at 0.866 are obtained with the proposed CBPWM method. Beside the study on the modulation method for the IMC, the development of the IMC topology is also concerned. In this research, a new IMC topology is proposed in order to supply dual three-phase loads.
The proposed converter is an emerging topology that integrates the five-leg inverter into the conventional three-phase to three-phase IMC topology. The CBPWM method suitable for the proposed IMC topology is also introduced. Simulation and experimental results are shown that the proposed converter can provide high quality input and output waveforms. vii To my parents: Nguyen Dinh To, Tran Thi Kim Bien To my beloved wife: Tran Thi Phuong Thao and to my sister and my brother: Nguyen Dinh Kim Giao, Nguyen Dinh Tuan viii Acknowledgements This work was carried out in Industrial Network and Power Electronics Laboratory (INPEL) at School of Electrical Engineering, University of Ulsan during the year 2007-2012.
This research was support by research fund of University of Ulsan and Network-based Automation Research Center (NARC). First of all, I would like to thank my supervisor, Professor Hong-Hee Lee, director of NARC at the University of Ulsan for his technical suggestions and invaluable support during of the course of my research. I express my sincere appreciation to the other members of committee: Professor Tae-Won Chun (University of Ulsan), Professor Heung-Geun Kim (Kyungpook Nat’l University), Professor Jin Hur (University of Ulsan) and Professor Jang-Mok Kim (Busan Nat’l University) for their valuable time, engagement and support. I am also thankful to all Professors in School of Electrical Engineering, University of Ulsan for their support and giving me knowledge.
In addition, I thank all members in INPEL for their friendship and providing the necessary help, both theoretical and practical, to carry out this research. I express my grateful for the personal grants from Brain Korea 21 Program and NARC. The financial support and metal assistant provided their grants have been of crucial important to me. Finally, I would like to thank my family and my dear wife for their infinite patience, support and love.
They helped me to regain enthusiasm, strength and determination during the difficult times. Ulsan, December 2012 Nguyen Dinh Tuyen ix Table of Contents Abstract .ix List of Figures. xiii List of Tables .1 Matrix Converter, State of the Art.2 Review Previous Works Related to IMC .4 Contributions of the Thesis .5 Outline of the Thesis. 11 Fundamentals of Matrix Converter .2 Hardware Implementation of MC .2 Over-voltage Protection.
Comparisons DMC and IMC .2 Reduced Number of Switches .3 Possibility of Constructing Several Direct Power Converter Topologies. 28 Control of Indirect Matrix Converter.1 Operating Principle of IMC .2 Rectifier Stage Control .3 Inverter Stage Control .5 Simulation and Experimental Results. 42 Space Vector Modulation Strategies to Reduce Common-Mode Voltage .3 Method I with the Voltage Transfer Ratio from 0 to 0.4 Method II with the Voltage Transfer Ratio from 0.5 Method III with Voltage Transfer Ratio less than 0.6 Output Voltage Performance Comparisons. 76 Carrier-Based PWM Method for Indirect Matrix Converter .2 Carrier-Based PWM Strategy for IMC .1 Rectifier Stage Control .2 Inverter Stage Control.
89 IMC Topology with Single Three-Phase Input and Dual Three-Phase Outputs .2 Operational Principles of the Proposed IMC Topology with Dual Three- phase Outputs .1 Rectifier Stage Control .2 Inverter Stage Control .3 Derivation of Voltage Transfer Ratio .4 Derivation of Input Currents and Output Voltages. 118 Conclusions and Future Works. 135 xii List of Figures Fig. DMC topology Fig.
IMC topology Fig. Bidirectional switch configurations (a) Diode bridge with single IGBT switch (b) Common emitter bidirectional switch (c) Common collector bidirectional switch (d) Anti-parallel reverse blocking IGBT switch (e)&(f) Series IGBT diode switch Fig. Filter configuration for MC Fig. A simplified two-phase to single-phase MC Fig.
Four-step current-based commutation diagram (a) Control signals Sad, Sar of the switch Sa and Sbd, Sbr of the switch Sb in four-step current-based commutation when output current is positive (b) Four-step switching diagram for two bi-directional switches Fig. Four-step voltage-based commutation diagram (a) Control signals Sad, Sar of the switch Sa and Sbd, Sbr of the switch Sb in four-step voltage-based commutation when vab is positive (b) Four-step switching diagram for two bi-directional switches Fig. The zero dc-link current commutation Fig. The clamp circuit of the DMC topology Fig.
The clamp circuit of IMC topology Fig. Different reduced switch number IMC topologies (a) Sparse matrix converter (b) Very Sparse matrix converter (c) Ultra sparse matrix converter Fig. Four-leg IMC Fig. Z-source IMC Fig.
Multi-drive system based on IMC topology with paralleled connection of two VSIs. Multi-drive system based on IMC topology with 9-switch VSI Fig. Three-level IMC Fig. Space vector diagram of the rectifier stage.
Input sector and switching state according to the input voltage. Space vector diagram of inverter stage. The switching pattern of MC. Simulation results of (a) Input voltage and current.
(b) dc-link voltage and current. (c) line-to-line output voltage and three-phase output currents waveforms of the IMC. Experimental results of (a) Input voltage and current. (b) Dc-link voltage and current.
(c) Line-to-line output voltage and three-phase output currents waveforms of the IMC. Leakage current path of IMC. Six sectors for rectifier stage. Space vector diagram of inverter stage in Method I.
The switching pattern to reduce CMV in IMC by using Method I. Space vector diagram of inverter stage in Method II. The switching pattern to reduce CMV in IMC by using Method II. The definition of input current sector in Method III.
Space vector diagram of rectifier stage in Method III. Space vector diagram of the inverter stage in Method III. Switching pattern to reduce CMV in IMC by using Method III. THD of the line-to-line output voltage according to voltage transfer ratio.
The effective CMV reduction algorithm flowchart. Dc-link voltage waveforms of IMC in two cases: (a) Proposed Method I and II. (b) Proposed Method III. (a) Three-phase input currents.
(b) Three-phase output currents. (c) Line-to-line output voltage. (d) FFT for line-to-line output voltage with conventional method for m=0. (a) Three-phase input currents.
(b) Three-phase output currents. (c) Line-to-line output voltage. (d) FFT for line-to-line output voltage with proposed Method I at m=0. (a) Three-phase input currents.
(b) Three-phase output currents. (c) Line-to-line output voltage. (d) FFT for line-to-line output voltage with proposed Method II at m=0. (a) Three-phase input currents.
(b) Three-phase output currents. (c) Line-to-line output voltage. (d) FFT for line-to-line output voltage with conventional method at m=0.4, fout=50Hz Fig. (a) Three-phase input currents.
(b) Three-phase output currents. (c) Line-to-line output voltage. (d) FFT for line-to-line output voltage with proposed method I at m=0. (a) Three-phase input currents.
(b) Three-phase output currents. (c) Line-to-line output voltage. (d) FFT for line-to-line output voltage with proposed method III at m=0.4, fout=50Hz Fig. CMV waveform at m=0.7, fout=50Hz with (a) Conventional method.
(c) Proposed method II. CMV waveform at m=0.4, fout=50Hz with (a) Conventional method. (c) Proposed method III. Dc-link voltage waveforms of IMC in cases xv (a) Proposed Method I and II.
(b) Proposed Method III. (a) Three-phase input currents. (b) Three-phase output currents. (c) Line-to-line output voltage.
(d) FFT for line-to-line output voltage with conventional at m=0. (a) Three-phase input currents. (b) Three-phase output currents. (c) Line-to-line output voltage.
(d) FFT for line-to-line output voltage with proposed Method I at m=0.7, fout=50Hz Fig. (a) Three-phase input currents. (b) Three-phase output currents. (c) Line-to-line output voltage.
(d) FFT for line-to-line output voltage with proposed Method II at m=0.7, fout=50Hz Fig. (a) Three-phase input currents. (b) Three-phase output currents. (c) Line-to-line output voltage.
(d) FFT for line-to-line output voltage with conventional method at m=0.4, fout=50Hz Fig. (a) Three-phase input currents. (b) Three-phase output currents. (c) Line-to-line output voltage.
(d) FFT for line-to-line output voltage with proposed Method I at m=0.28 (a) Three-phase input currents. (b) Three-phase output currents. (c) Line-to-line output voltage. (d) FFT for line-to-line output voltage with proposed Method III at m=0.7, fout=50Hz Fig.
(b) Its FFT with conventional method at m=0. (b) Its FFT with proposed Method I at m=0. (b) Its FFT with proposed Method II at m=0.7, fout=50Hz Fig. (b) Its FFT with conventional method at m=0.4, fout=50Hz Fig.
(b) its FFT with proposed Method I at m=0. (b) its FFT with proposed Method III at m=0.4, fout=50Hz Fig. (a) The timing of modulated switches. (b) Switching state according to the carrier and modulation signals for rectifier stage in sector 1.
(a) The switching state of three upper switches in the inverter stage. (b) The waveform of modulation signals and carrier signal. (c) The generation of gate signal for the switch SA Fig. The block diagram of the carrier-based PWM generator for the inverter stage Fig.
The block diagram of the proposed CBPWM modulation based on the DSP and FPGA Fig. Experimental PWM signals for the modulated switch in rectifier stage (Sbn) and three upper switches in the inverter stage (SA, SB, SC) Fig. The experimental PWM signals for six bidirectional switches of rectifier stage Fig. The dc-link voltage (vdc) and its average value ( Vdc ) Fig.
The input waveforms of the IMC Fig. The output waveforms of IMC Fig.