VIETNAM NATIONAL UNIVERSITY HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING BUI XUAN VIET ANH LE TRONG TRUNG CAPSTONE PROJECT UNG DUNG SCAN COMPRESS DE GIAM SO LƯỢNG SCAN IO VA TEST TIME Test cost reduction for Scan IOs and test time with scan compression techniques in DFT ENGINEER OF COMPUTER ENGINEERING HO CHI MINH CITY,2021 VIETNAM NATIONAL UNIVERSITY HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING BUI XUAN VIET ANH- 15520013 LE TRONG TRUNG- 16521834 UNG DUNG SCAN COMPRESS DE GIAM SO LƯỢNG SCAN IO VA TEST TIME Test cost reduction for Scan IOs and test time with scan compression techniques in DFT ENGINEER OF COMPUTER ENGINEERING SUPERVISOR PhD. NGUYEN MINH SON M. NGUYEN DUY MANH THI HO CHI MINH CITY, 2021 THONG TIN HOI DONG CHAM KHÓA LUẬN TOT NGHIỆP Hội đồng chấm khóa luận tốt nghiệp, thành lập theo Quyết định số " ngây. của Hiệu trưởng Trường Đại học Công nghệ Thông tin.
VIETNAM NATIONAL UNIVERSITY, SOCIALIST REPUBLIC OF VIET NAM HO CHI MINH CITY Independence - Liberty — Happiness UNIVERSITY OF INFORMATION TECHNOLOGY CAPSTONE PROJECT Title: Ung dung scan compress để giảm số lượng scan IO và test time. Project’s name: Test cost reduction for Scan IOs and test time with scan compression techniques in DFT. Nguyen Minh Son M.S Nguyen Duy Manh Thi Duration: From Sep 21* 2020 to Jan 8° 2021 Students: Bui Xuan Viet Anh - 15520013 Le Trong Trung - 16521834 e Overview: The first ICs were tested with test vectors created by hand. It proved very difficult to get good coverage of potential faults, so Design for Testability (DFT) based on scan and automatic test pattern generation (ATPG) were developed to explicitly test each gate and path in a design.
These techniques were very successful at creating high-quality vectors for manufacturing test, with excellent test coverage. However, as chips got bigger the ratio of logic to be tested per pin increased dramatically, and the volume of scan test data started causing a significant increase in test time, and required tester memory. Scan Compression is a technique used to reduce the time of testing integrated circuits. e Purpose: Using Scan Compress technique to improve test time and reduce resources in DFT.
e Methodology: - Research on Scan Compress. - Research on Codec. - Collect material for setting Scan environment. - Experiment and evaluate parameters.
- Collect result and compare. - Write final report. e Project contents: Step 1: Research on Scan Compress. - Have enough knowledge about Scan Compress.
- Find out how Scan Compress effect on our. Step 2: Research on Codec. - Learning about Compressor and Decompressor. - Estimate the benefit when applying Codec into Scan step.
> Result: know basic architecture of Codec, find the way to use it on design. Step 3: Collect material for setting Scan environment. - Using NAND block of SNST as sample for using Scan Compress on. - Read sample netlist (Verilog code, library, .) and research sample Scan environment.
- Define Verilog code to implement on our own block. Step 4: Experiment and evaluate parameters. - Implement Internal Scan and Compress Scan in same design. - Changing number of I/O Scan, using “compress ratio” in Compress Scan.
Step 5: Collect result and compare. After trial two experiments with two difference corners on same design, we evaluate the detail parameters between them: - Scan Compress: have larger area overhead, more numbers of scan chain but more importantly it makes chains shorter than Internal Scan. - Two types of Scan have almost same Test Coverage, but test time is reduced many times. Step 6: Write final report e Limitation: - This is a fairly new field for us so in the presentation of specialized words certainly cannot avoid confusing errors.
- Because the data of the design is not yet finished, we do not have a license for ATPG (TMAX tool) so the result cannot be shown in more detail. e Expected results: - Since the scan chain length is shorter in Compress Scan, but the pin count is identical, we get lower Test Time. - Reduce test time by 9 to 10 times. Project Planning: No Content Student Duration Note 07/09/2019 - 1 | Research Scan Compress | Bui Xuan Viet Ani 30/09/2019 Research ORCA Bui Xuan Viet An 01 /1 0/ 20 1/10/2020 20 - 2 Le Trong Trung 20/10/2020 Collect material for Bui Xuan Viet An 21/10/2020 - 3 setting Scan environment Le Trong Trung 14/11/2020 4 Experiment and evaluate | Bui Xuan Viet An! 15/11/2020 - parameters Le Trong Trung 30/11/2020 Collect result and 01/12/2020 - 5 Bui Xuan Viet Anh compare between them 14/01/2021 Bui Xuan Viet Anh | 15/12/2020 - 6 Write final report Le Trong Trung 05/01/2021 Confirm of instructor 1 HCM City, 24" Jan 2021 (Signature and full name) Students (Signature and full name) Confirm of instructor 2 (Signature and full name) PREFACE First of all, we would like to express our sincere thanks to all the teachers and students of the University of Information Technology — Vietnam National University Ho Chi Minh city, especially the teachers of Computer Engineering, who have facilitated us to learn a lot of knowledge and experience throughout the learning period.
In particular, we would like to sincerely thank Dr. Nguyen Minh Son and Mr. Nguyen Duy Manh Thi who have guided our group very enthusiastically throughout the course of the project, supporting and providing us with valuable knowledge so that our group can complete the topic well. Moreover, we would also like to thank our friends, colleagues who have helped us to improve our project, to exchange and solve our problem conscientiously during implement the thesis.
Last but not least, we would like to thank our parents for always creating favorable conditions and spiritual support throughout the course of the dissertation. Despite great efforts, our knowledge and experience are still limited, so the report can not avoid many shortcomings. We are looking forward to receiving many comments from teachers Once again, we would like to sincerely thank you! Ho Chi Minh City, 24 December 2020 Students Bui Xuan Viet Anh Le Trong Trung THESIS SUMMARY In recent decades, the microelectronics industry has made rapid progress thanks to its high-density, integrated lead technology. The development of micro- electronic technology is favorable conditions for other industries to develop such as Information Technology, Telecommunications Electronics,.
and especially in every consumer electronic product has the contribution of microelectronic technology. With many applications as above, the research of integrated microchip technology - Application-Specific Integrated Circuits (ASICs) is very necessary for the current period especially in our country, so I have implemented the topic “Design for Test design for signal processing chip”. The topic covers the basics of the application-oriented integrated circuit design process (System on Chip flow). The topic delves into the research and application of DFT (Design for Test) techniques to ensure the ability to test silicon faults, also known as manufacturer- made faults for chips after they have been produced.
Through the process of implementing the topic, we have understood the basic knowledge of micro-circuit design technology as well as related micro- electronic knowledge. The topic is done with a serious working attitude and best efforts, but this is a new field, knowledge is limited so it is impossible to avoid faults. We look forward to receiving the comments of teachers and friends to improve the topic. TABLE OF CONTENTS PREFACE us essssssssssssssenecssenensssneneseesesenesenenesessesesenenenesenesseseseseneasnssesseseseneaenenenes 8 THESIS SUMMARY .scssssssssssesesssssnssesssseenenessssseneeseneneneasseneseseseseaeaesesenenseaes 9 FIGURE LLIST.
5-5-5 se SeEEtEtEtetetetrrrrrrkererrkrkrerrsrrerrree 13 TABLE LIST IPEEES. 15 LIST OF ABBREVIATION. INTRODUCTION ABOUT DESIGN FOR TESTABILITY (DFT) & CONCEPTS. Design for Testability.
Scan Insertion flow. Create Test PTOfOCOI. ¿c1 tk ngàn HH HH it 5. Scan ATChif€C{UT.
Insert Scan Path. DFT DRC COV€TAB6. (11T nn HT HH Hi 5 2. -- + +5 1 tt 1 HH HH ty 6.
Example Scan Insertion SCTipI. Concepts in the DFT method. What is Scan Technique 3. Scan Insertion Technique.
Modeling silicon faults. Fault Coverage, Test COVeTAE€. t2 HH HH 110101012 re. Scan Signals and Some Problems Applying Scan Insertion.
Automatic Test Pattern Generation ATPG. SCAN COMPRESSION TECHNIQUE. Why we use Compression?. How Compression WOrks.
Test Compression Concepts. Test cycle SAVINBS. Ác TT HH Hiện 24 2. EXPERIMENT ON DATA LAB “ORCA”.- SH HH HH HH gu 00g e 27 3.
ORCA’s configuration lOgIC. Input and environment to run đata. Design Compiler and Design Vision 'T00Ì. Read a design into Design Vision.
Tool Design Compiler and Design Vision. Cell name and ref name. Zoom into examine the schematic. Apply Scan Compression for data lab “OIRCA'”.
Where to apply Scan Compression?. How to apply Scan Compression?. Report DFT_DRC Violations. Ăn HH nhung gu grêp 39 4.- ¿c1 HH HH HH HH Hi, 39 4.
Period of all CÏOCKS. Limitations of the topic. Development direction of the fOpÍC. Improvement of our project .cscscsessssssesenesesesscsesenesnscsenesesenseseneseseneeseneaeneseseneseseseeseneneneees 45 FIGURE LIST Figure 1.
Design using Boundary Scan Design. Design using Memory BIST. Design using BIST LOgIC. -------- 252525252 se£scserrersrsrse Figure 1.
Scan Insertion Process. -¿- + ¿+ 1k E9 HH ni, 4 Figure 1. Design before and after applying Scan [Š]. Non-scan Flip Flop.
Multiplexer Flip Flop. cece eee 5c S1 SE 2E Figure 1. Multiplexer Master-SÏavVe. Operation of two clock signals [3].
Scan Cell as Clocked Scan for Flip Flop. Scan Cell as Clocked Scan for Latches. Pa Ne el a "xe. ác 1n TT TH HT Hàn Hư Figure 1.
Partion Scan in Design.-- + (c1 * ng it Figure 1. Scan chain in a block (Partition A) [3]. Clock through Clock Gating [4]. Clock signal via Clock Gating processed [4].
Clock signals shifted through many logics [4]. Clock signals go through multiple processed Logics [4]. Clock signals used as data [4]. Uncontrollable reset signal [5].
ccc eeeeseeeeeeseeeeeeneeseeeeneeees Figure 1. Uncontrollable Clr signal [Š]. Asynchronous sync able reset signal processing compiler cannot be controlled. Asynchronous syncable clear signal processing compiler can not be controlled.
Test pattern Compression Needed. Differences between two scan mode [6]. Example for Test Cycle Savings. Compressor Logic Structure Example for 8-to-4 Compressor [7].
Decompressor Logic Structure Example for 4-to-8 Decompressor [7] —. ORCA 1C05 FPGA Die .--- ¿5c St ttetrtereererrrerree 27 Figure 3. ORCA_ TOP structure (RTL code).---- eee +s+++s<sc+c+++++++ 30 Figure 3. Explore the Design.
Cell name and ref name ÏiS(. Zoom options in Design Vision. ORCA_TOP module with Internal ScanIn. ORCA_TOP module with Compression Scanln.
Command to change Scan mode. Command to choose number of Scan Chain. Flow chart of project. DFT_DRC Figure 4.
Preview_dft Internal Scan mode. Preview_dft Compress Scan mode. Preview_dft Compress Scan mode. Period of all clocks in ORCA is 100ns.
Real test cycle saving. TABLE LIST Table 1. Two modes of operation of Multiplexer Latch Master-Slave [2]. Clocked Scan's two operating modes for latches [2].
Compare table of two techniques. LIST OF ABBREVIATION ABBREVIATION FULL MEANING ATE Automatic Test Equipment ATPG Automatic Test Pattern Generation BIST Built-in Self Test DFT Design for Testability DRC Design Rule Checks FC Fault Coverage FPGA Field Programmable Gate Array FM Frequency Modulation IC Intergrated Circuit LSSD Level Sensitive Scan Design ORCA Optimized Reconfigurable Cell Array RTL Register Transfer Level SoC System on Chip TATR Test Application Time Reduction TC Test Coverage TDVR Test Data Volume Reduction Chapter 1. ` INTRODUCTION ABOUT DESIGN FOR TESTABILITY (DFT) & CONCEPTS 1. Design for Testability 1.
General Nowadays, as the size and complexity of integrated circuits (IC) increase, fault checking becomes more difficult. DFT technique allows designers to create products with the highest reliable fault checking and most time-saving capabilities. Scan compression was introduced in the year 2000 and has seen rapid adoption.