NANYANG TECHNOLOGICAL UNIVERSITY Techniques for Multi-Standard Cognitive Radios on FPGAs Pham Hung Thinh School of Computer Engineering A thesis submitted to Nanyang Technological University in partial fulfilment of the requirements for the degree of Doctor of Philosophy September 2015 Acknowledgments It is great pleasure to me in expressing my gratitude to all those people who have continuously supported me and had their contributions in making this thesis possible. I would like to express my sincere thanks and appreciation to my supervisors, Prof. Suhaib Fahmy, and Prof. Ian McLoughlin for giving me constant trust during the entire research of my Ph.
studies, for their helpful suggestions and advices, for their continuous support and their teachings essential to achieve this objective. I express my sincere gratitude towards Prof. Samarjit Chakraborty at Institute for Real-Time Computer Systems, TU Munich for providing me an internship opportunity in the final stage of my PhD. I also wish to thank all colleagues and technical staffs in CHiPES for their prompt support and helpful in providing all the facilities required for my research work.
Last but not least, I would like to acknowledge my family in Viet Nam, for their constant love and encouragement. i Abstract The thesis explores techniques for enabling cognitive radio design on field pro- grammable gate arrays (FPGAs). We demonstrate the strengths of FPGAs in offering a high throughput, low-power baseband platform, and develop a flexi- ble Orthogonal Frequency Division Multiplexing (OFDM) baseband chain with high-level control and support for multiple standards. We present contributions in OFDM synchronisation to enable more robust radios in harsher channels, and tolerating less precise RF components.
We also present a novel technique for managing out of band leakage to enable more efficient spectral use in a dynamic spectrum allocation setting. For each of these approaches, we design, optimise, and characterise working hardware implementations of the required modules, with a focus on flexibility and low power. Finally, we present an approach for apply- ing FPGA partial reconfiguration to minimise reconfiguration time when a radio switches modes, allowing intermediate data to be buffered and processed after re- configuration is complete. These contributions form an important foundation in building a fully functional prototyping platform for cognitive radio systems.
ii Contents Acknowledgments. ii List of Abbrevations xi List of Notation .1 Cognitive and Software Defined Radio .1 Multi-Standard Cognitive Radios .2 Existing Radio Platforms .2 Orthogonal Frequency Division Multiplexing .2 OFDM Radio Systems .5 Shaping OFDM Spectral Leakage .1 Spectrum Emission Masks in Recent Standards .2 Dynamic Channel Requirements .3 Filtering in OFDM Implementations .3 Field Programmable Gate Arrays .1 FPGAs for Radio Platforms .2 Power Dissipation on FPGA .3 Power Estimation Tools. 43 iii CONTENTS iv 3 Multiplierless Correlator Design for OFDM Timing Synchronisa- tion 44 3.1 Design of DSP48E1 Based Correlator .2 Design of Multiplierless Correlator .3 Simulation and Discussion. 55 4 Method for OFDM Timing Synchronisation 56 4.1 Coarse STO and Fractional CFO Estimation .2 Fractional CFO Compensation .3 Fine STO Estimation .3 Proposed Fractional CFO Estimation and Synchronisation .1 Frame Synchronisation and Fractional CFO Estimation .2 Fractional CFO Compensation .3 Simulation Results and Discussion .1 Performance in AWGN .2 Performance in Fading Channels .3 Performance with Large Frequency Offset .1 Implementation of Conventional Synchroniser .2 Implementation of Proposed Synchroniser .3 Effect of Reduced Precision.
82 5 IFO Estimation Method for OFDM Frequency Synchronisation 83 5.3 Enhanced OFDM Synchronisation Through Novel IFO Estimation Architecture. 105 CONTENTS v 6 Spectrum Efficient Shaping Method for OFDM Cognitive Radios106 6.2 Signal Model for Spectral Leakage Filtering .11p Signal and Channel Models .11af Signal and Channel Models .2 Image Spectrum Cancellation By FIR Filter .4 Proposed Spectrum Efficient Shaping Method .1 New Spectral Leakage Filtering Method .2 Novel CR Filtering Architecture .5 Simulation Results and Discussion .1 Configuration and Performance Evaluation for 802.2 Configuration and Performance Evaluation for 802.11af Spectral Efficiency. 129 7 An Architecture for Multi-Standard Cognitive Radios 131 7.3 Proposed OFDM Baseband for MSCR .4 Fine STO Estimation .5 Remove Cyclic Prefix .7 IFO Estimation and Channel Equalisation .9 Data symbol demodulation (DatSymDem) .4 Performance Analysis and Discussion .1 Latency and Stalling for PR-Based Baseband .2 Analysing the Proposed OFDM MSCR Approach. 159 8 Conclusions and Future Work 161 8.1 Summary of Contributions .1 Robust, Efficient Synchronisation .2 OFDM Spectrum Shaping .3 Multi-Standard Radio Design .2 Future Research Directions .1 Increasing Spectrum Efficiency with Shaping for NC-OFDM 163 8.2 Efficiently Adaptive Shaping Spectral Leakage .3 Standardised Software Interface for Multi-Standard Radio Platform .4 Alternative MultiCarrier Modulations Techniques .5 Higher Layer Knowledge to Minimise Reconfiguration Time 165 8.
165 Bibliography 166 List of Figures 2.1 Block diagram of a multicarrier modulated system, (a) in the countinuous- time and (b) in discrete-time .2 The spectrum of subcarriers in OFDM [1].3 OFDM transmission without cyclic prefix results in ISI among ad- jacent symbol.4 OFDM transmission with cyclic prefix avoids ISI among adjacent symbol.5 Inserting Cyclic Prefix in the OFDM symbol.6 An OFDM system model.7 Block diagram of an OFDM radio system.8 OFDM received symbol with timing offsets of -1, 1, -5 and 5 in a, b, c, d, respectively.9 Inter carrier interference (ICI) caused by frequency offset ∆f .10 The constellations of OFDM received symbol with frequency offets of 0.25 sub-carries spacing in a, b, c, d, respectively.11 The constellations of 5 consecutive OFDM received symbols with frequency offsets of 0.12 The constellations of an OFDM received symbol and 5 consecutive OFDM received symbols with phase noise variance of 0.25 rad2 in (a), (b) respectively.13 The comparison between TVBD SEM and 802.14 The comparison between traditional and DUC Front-end.1 Downlink preamble symbols for IEEE 802.2 Transposed direct form correlator.3 Structure of DSP48E1 block inside the Virtex-6 [2].4 Pipeline structure of the complex number multiply-add.5 Pipeline structure of correlator using DSP48E1 blocks.6 Structure of multiplierless correlators.7 Correlator power consumption at different frequencies.8 Correlator output with SNR = 10 dB.9 Detection failure rate with increasing SNR.1 The timing metric in [3] applied to the IEEE 802.16-2009 preamble in an AWGN channel (SNR = 10dB). 58 vii LIST OF FIGURES viii 4.2 The timing metric in [4] applied to the IEEE 802.16 preamble in an AWGN channel (SNR = 10dB) .3 Proposed timing metrics applied to the IEEE 802.16 preamble in AWGN (SNR = 10 dB, CFO = 10.4 The synchronisation flow according to the received samples within the preamble showing its packet format above the conventional syn- chronisation scheme flow (middle), and proposed scheme (bottom). With the packet timing illustrated above.5 Performance of the frame synchronisation method versus the selec- tion threshold for an AWGN channel (with SNR =10dB).6 Performance of time synchronisation in AWGN channels with a fre- quency offset of 0.7 Performance of fractional frequency offset estimation in AWGN channels.8 Frame synchronisation performance of various methods in an SUI1 channel with respect to SNR.9 Frame synchronisation performance of various methods in an SUI2 channel with respect to SNR.10 Performance of frame synchronisation in an AWGN channel with uniform random frequency offset varying from -10 to 10 times carrier spacing, with respect to SNR.11 Architecture of the conventional synchronisation FPGA implemen- tation.12 Architecture for the proposed synchronisation method implemented on FPGA.13 Implementation of energy correlator on FPGA.14 Performance of CFO estimation in an AWGN channel against SNR, with different numbers of fractional bits used in the computation of P 0.15 Performance of frame synchronisation in an AWGN channel against SNR, with different numbers of fractional bits used in the compu- tation of R0 .1 Baseband processing block diagram.2 Pilots in the long preamble of IEEE 802.3 Circuit for the known-pilots shift register.4 Resource sharing approach for computing V˜.5 Architecture of proposed IFO estimator.6 Fail rate of IFO estimation methods in AWGN channel without RTO.7 Fail rate of IFO estimation methods in AWGN channel with RTO.8 Fail rate of IFO estimation methods in SUI1 channel.9 Fail rate of IFO estimation methods in SUI2 channel.10 Fail rate for different wordlengths in AWGN channel without RTO.11 Fail rate for different wordlengths in AWGN channel with RTO.12 Fail rate for different wordlengths in SUI1 channel. 100 LIST OF FIGURES ix 5.13 Fail rate for different wordlengths in SUI2 channel.14 DSP block based 3-input adder for correlation.1 Pulse Shaping operation performed on OFDM symbols.2 Spectral envelope due to pulse shaping OFDM symbols using three smoothing functions and different roll-off factors for 802.
Class C and D spectral emission mask limits are overlaid as dotted lines.11p OFDM symbols shaped with different window functions, with the image spectrum included.4 Spectra of OFDM symbols for 802.11p using different FIR interpo- lation filters, with L = 8.5 The CR-Based architecture for adaptive OFDM spectral leakage shaping.11p signal of the proposed CR architecture after interpolation.11p signal using option Prop1 with 20th order FIR filtering.11p signal for Prop2 with 12th order FIR filtering.11af signal using the proposed CR architecture.10 Fitting Filtered Spectrum of 802.11af signal to SEMs.1 The structure of a generic MSCR system .2 The receiver FIFO module.3 Block diagram of Synchronisation module.4 Block diagram of frequency compensation module.5 Block diagram of fine STO estimation module.6 The block diagram of IFO estimation and channel equalisation .7 Block diagram of phase tracking module.8 Comparison of reconfiguration latency for a single and multiple PR modules.9 Bitstream sizes for PR modules.10 The latency of sub-modules for three standards .11 The configuration time and latency of sub-modules for OFDM- based MSCR system .12 A scenario of a transmission .13 The halting time comparison of the system for three different ap- proaches.14 A comparison of the three approaches in terms of system reconfig- uration latency and FIFO requirements.16 Block diagram of verified system .17 The verification results of the transmitter.18 Verification results of the receiver.19 Verification results of the baseband system. 159 List of Tables 3.1 Resource utilisation summary.2 Correlator power consumption at 50 MHz.1 Resources required for computing P 0 on FPGA with different word lengths, Q1.2 Resources required for computing R’ on FPGA with different word lengths, Q1.3 Total resources consumed by a full word length implementation of SoA and four reduced complexity instances of the proposed method. Dynamic (Dpwr) and quiescent power (Qpwr) consumption are re- ported in mA. Maximum frequency is reported in MHz.4 Resource comparison between two synchronisation methods.1 Resource utilisation and dynamic power of IFO estimators.1 Major parameters of 802.11af OFDM PHYs .2 Popular window-based FIR filter lengths .3 Hardware Usage for spectral shaping .1 System specifications of three supported OFDM-based standards.2 Parameterised values according to supported standards .3 Allocation vector coding.22 OFDM-based implementation .
