UNIVERSITY OF CALIFORNIA Santa Barbara Communication Transceiver Design with Low-Precision Analog-to-Digital Conversion A Dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Electrical and Computer Engineering by Jaspreet Singh Committee in Charge: Professor Upamanyu Madhow, Chair Professor Shiv Chandrasekaran Professor Jerry Gibson Professor Joao Hespanha Professor Kenneth Rose December 2009 The Dissertation of Jaspreet Singh is approved: Professor Shiv Chandrasekaran Professor Jerry Gibson Professor Joao Hespanha Professor Kenneth Rose Professor Upamanyu Madhow, Committee Chairperson November 2009 Communication Transceiver Design with Low-Precision Analog-to-Digital Conversion c 2009 Copyright ° by Jaspreet Singh iii To my parents and my brother iv Curriculum Vitæ Jaspreet Singh EDUCATION Dec 2009 Ph. Electrical and Computer Engineering University of California, Santa Barbara Sep 2009 M. Statistics University of California, Santa Barbara Dec 2005 M. Electrical and Computer Engineering University of California, Santa Barbara May 2004 B.
Electrical Engineering Indian Institute of Technology, Delhi PUBLICATIONS Journal Articles • J. Madhow, “On the limits of communication with low- precision analog-to-digital at the receiver”, IEEE Transactions on Communications, vol. Cagley, “Multiple target tracking with binary proximity sensors”, submitted to ACM Transactions on Sen- sor Networks. Madhow, “Multi-gigabit communication: the ADC bottleneck”, (invited paper), Proc.
on UltraWideband, Vancou- ver, Canada, September 2009. Madhow, “On block noncoherent communication with low-precision phase quantization at the receiver”, Proc. on Information The- ory (ISIT’09), Seoul, Korea, July 2009. Madhow, “Optimization of correlated source coding for event-based monitoring in sensor networks”, Proc.
IEEE Data Com- pression Conf. (DCC’09), Snowbird, USA, March 2009. Madhow, “Signal processing for multi-gigabit commu- nication”, (invited paper), Proc. Information Theory and Applications Workshop (ITA’09), San Diego, USA, February 2009.
Madhow, “Capacity of the discrete-time AWGN chan- nel under output quantization”, Proc. on Information Theory (ISIT’08), Toronto, Canada, July 2008. Cagley, “Tracking multiple targets using binary proximity sensors”, Proc. ACM/IEEE Intl.
on Information Processing in Sensor Networks (IPSN’07), Cambridge, USA, April 2007. Madhow, “Communication limits with low-precision analog-to-digital conversion at the receiver”, Proc. on Commu- nications (ICC’07), Glasgow, Scotland, June 2007. Madhow, “On the limits of communication perfor- mance with one-bit analog-to-digital conversion”, Proc.
IEEE Workshop on Signal Processing Advances in Wireless Communication (SPAWC’06), Cannes, France, July 2006. Madhow, “Signal processing with low-precision A/D conversion: a framework for low-cost gigabit wireless communication”, Poster Pre- sented at IEEE Communication Theory Workshop (CTW’06), Puerto Rico, USA, May 2006. vi Abstract Communication Transceiver Design with Low-Precision Analog-to-Digital Conversion by Jaspreet Singh As communication systems scale up in speed and bandwidth, the cost and power consumption of high-precision (e., 10–12 bits) analog-to-digital converter (ADC) becomes the limiting factor in modern receiver architectures based on dig- ital signal processing. One possible approach to relieve this ADC bottleneck is to employ a low-precision (e.
This may be suitable for applications requiring limited dynamic range, such as line-of-sight communication using small constellations. However, the drastic reduction of ADC precision raises funda- mental questions, at both information-theoretic and algorithmic levels, regarding whether it is even possible to engineer a communication link with such a signif- icant nonlinearity so early in the receiver processing. In this thesis, we present results from our efforts towards answering some of these questions. We first investigate the Shannon-theoretic limits of communication imposed by the choice of low-precision ADC, for transmission over the ideal real additive white Gaussian noise channel.
For an ADC employing K quantization bins (i., a precision of log2 K bits), we prove that the channel capacity can be achieved vii using a discrete input distribution with at most K+1 support points. A joint optimization over the choice of the input and the quantizer is performed, and the obtained numerical results reveal that at SNR up to 20 dB, the use of 2-3 bit ADC incurs a loss of only about 10-15 % in capacity compared to unquantized observa- tions. Furthermore, we observe that a sensible choice of uniform pulse amplitude modulated input, with quantizer thresholds set to perform maximum likelihood hard decisions, achieves performance close to that attained by an optimal input and quantizer pair. We then turn our attention to the problem of carrier synchronization using low-precision ADC.
We focus on a block noncoherent channel model, wherein the phase rotation caused by a small frequency offset, although a priori unknown, can be approximated as constant over a block of symbols. For M-ary phase shift keyed (M-PSK) inputs, the performance of phase-only quantization, which is attractive due to its ease of implementation, is investigated. The symmetry inherent in the resulting phase-quantized channel model is exploited to obtain low-complexity al- gorithms for channel capacity computation and block noncoherent demodulation. Numerical results, quantifying the channel capacity, and the uncoded error rates, are obtained for QPSK input with different number of phase quantization sectors and different block lengths.
Dithering the constellation is shown to improve the performance in the face of drastic quantization. viii Contents Curriculum Vitæ v Abstract vii List of Figures xi List of Tables xiii 1 Introduction 1 1.2 Signal Processing with Low-Precision ADC .1 Discrete Memoryless Channels .2 Continuous Alphabet Channels .4 Recent Related Work. 20 3 The AWGN-Quantized Output Channel 22 3.1 Structure of Optimal Inputs .2 Optimality of a Discrete Input .3 Symmetric Inputs for Symmetric Quantization .4 1-bit Quantization: Antipodal Signaling is Optimal .1 Cutting-Plane Algorithm .2 Duality-based Upper Bound .3 Comparison with Unquantized Observations .4 Additive Quantization Noise Model .1 Open Technical Issues. 53 4 Carrier Synchronization with Low-Precision ADC 55 4.1 Block Noncoherent Communication .2 Channel Model and Receiver Architecture .3 Input-Output Relationship .4 Efficient Capacity Computation .5 Block Noncoherent Demodulation .1 Directions for Future Work .1 Achievability of Capacity .3 Proof of Proposition 2 .4 Convexity of the Function h(Q( y)).
101 x List of Figures 1.1 Modern DSP-centric receiver design. Does it scale to multi-Gigabit per second speeds ? .2 QPSK input and 8-sector phase quantization .1 ADC technology trends published in Walden’s survey [1]. The vari- ous curves depict the fundamental limitations on the achievable precision imposed by different non-idealities.1 Probability mass function of the optimal input generated by the cutting-plane algorithm [2] at various SNRs, for the 2-bit symmetric quantizer with thresholds {−2, 0, 2}.2 The left-hand side of the KKT condition (3.7) for the input dis- tribution generated by the cutting-plane algorithm (SNR = 5 dB). The KKT condition is seen to be satisfied (up to the numerical precision of our computations).3 2-bit symmetric quantization : channel capacity (in bits per chan- nel use) as a function of the quantizer threshold q.4 2-bit symmetric quantization : optimal input distribution (solid vertical lines) and quantizer thresholds (dashed vertical lines) at various SNRs.5 Capacity plots for different ADC precisions.
For 2 and 3-bit ADC, solid curves correspond to optimal solutions, while dashed curves show the performance of the benchmark scheme (PAM input with ML quan- tization).1 Correction for frequency offset. (a) For high-precision ADC, the correction is done in the digital domain. (b) For low-precision ADC, it may be possible to perform analog offset correction based on digital feedback.2 Receiver architecture for 8-sector quantization.3 QPSK with 8-sector quantization (i. a) depicts how the unknown channel phase φ results in a rotation of the trans- mitted symbol (square : original constellation , circle : rotated con- stellation).
(b) and (c) depict the circular symmetry induced in the conditional probability P(z|x, φ) due to the circular symmetry of the complex Gaussian noise. (b) shows that increasing φ by 2π/K = (π/4) and z by 1 will keep the conditional probability unchanged, i. (c) shows that increasing x by 1 and z by 2 = (K/M ) will keep the conditional probability unchanged, i.4 Symbol error rate performance for QPSK with 8-sector phase quan- tization (left figure) and 12-sector phase quantization (right figure), for block lengths varying from 2 to 8. Also shown for comparison are the curves for coherent QPSK, and noncoherent unquantized QPSK.5 Ambiguity in the block noncoherent demodulator.
If the received vector is Z = [1 0], then (X = [0 0], φ = 0), and, (X = [0 3], φ = π4 ) are both equally likely solutions.6 (a) Standard PSK : the same constellation (the one shown) is used for both symbols in the block. (b) Dithered-PSK : the constellations used for the two symbols are not identical, but the second one is a dithered version of the first one.7 Performance comparison for QPSK with block length L = 6 : plots depict the capacity of the block noncoherent channel without quantiza- tion, and with 8-sector quantization (with and without dithering). Also shown is the capacity for coherent QPSK.8 Performance comparison for QPSK : plots depict the capacity of the coherent channel, unquantized block noncoherent channel (different block lengths), and the 12-sector quantized block noncoherent channel (different block lengths).1 The second derivative of h(Q( y)) is positive for small values of y. 101 xii List of Tables 3.1 Duality-based upper bounds on channel capacity, compared with the mutual information (MI) achieved by the distributions generated using the cutting-plane algorithm.2 Performance comparison : For 1, 2, and 3−bit ADC, the table shows the mutual information (in bits per channel use) achieved by the optimal solutions (denoted OPT), as well as the benchmark solutions (denoted BM).
Also shown are the capacity estimates obtained by as- suming the additive quantization noise model (AQNM). (Note that for 1-bit ADC, the benchmark solution coincides with the optimal solution, and hence is not shown separately.) The last column shows the unquan- tized AWGN channel’s capacity.3 SNR (in dB) required to achieve a specified spectral efficiency with different ADC precisions. 51 xiii Chapter 1 Introduction The last decade has witnessed rapid mass market deployment of cellular and wireless local area network communication systems. This has been propelled by the economies of scale provided by the low-cost integrated circuit implementation of sophisticated digital signal processing (DSP) algorithms that perform the bulk of the receiver functionalities, such as synchronization, channel estimation and equalization, demodulation and decoding.
An integral component of such DSP- centric receiver architectures is the analog-to-digital converter (ADC), which con- verts the received analog waveform into the digital domain with a sufficiently high precision (Fig. As we look to scale this DSP-centric design philosophy to higher speeds and bandwidths (to achieve data rates of the order of multi-Gigabit per second), the ADC becomes a bottleneck: high-speed high-precision ADC is either not available, or is costly and power-hungry [1]. On the other hand, the continuing progress of Moore’s “law” [3] implies that the integrated circuit im- 1 Chapter 1. Introduction Received RF Signal RF Amplifier Mixer / Filter ADC DSP Synchronization Equalization Demodulation & Decoding Figure 1.1: Modern DSP-centric receiver design.
Does it scale to multi-Gigabit per second speeds ? plementation of DSP algorithms is expected to continue to scale up in speed and down in cost. It is of interest, therefore, to explore the feasibility of DSP-centic transceiver design with low-precision ADC at the receiver. The conventional approach to transceiver design, when the available ADC pre- cision is high enough (10–12 bits or more), is to perform the design assuming that the ADC has infinite precision, and to then conduct simulation tests to obtain the algorithmic refinements needed to accommodate the effects of finite precision. This paradigm for design and implementation is predicated on the assumption that the performance with high-precision quantization essentially replicates that with infinite precision.
For drastically quantized systems (1–4 bits), this paradigm breaks down, since the effect of such severe quantization is expected to be fun- damentally different from that of high-precision quantization. This mandates a comprehensive rethinking of the system design, ranging from a Shannon-theoretic 2 Chapter 1. Introduction investigation to the design of new algorithms for performing the various receiver operations, with the starting assumption that the ADC used at the receiver has low-precision. In this thesis, we present results obtained from our efforts towards building such an understanding of the impact of low-precision ADC.
We focus attention on transmission over the classical bandlimited additive white Gaussian noise (AWGN) channel model.