VIETNAM NATIONAL UNIVERSITY HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING NGUYEN THANH CONG PHAM QUOC HUY GRADUATE THESIS STATIC TIMING ANALYSIS (STA) FOR ARM CORTEX M0 PHAN TÍCH THOT GIAN TĨNH (STA) CHO THIET KE ARM CORTEX M0 FACULTY COMPUTER ENGINEERING HO CHI MINH CITY, 2021 VIETNAM NATIONAL UNIVERSITY HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING NGUYEN THANH CONG- 17520298 PHAM QUOC HUY- 17520587 GRADUATE THESIS STATIC TIMING ANALYSIS (STA) FOR ARM CORTEX M0 PHAN TÍCH THỜI GIAN TĨNH (STA) CHO THIET KE ARM CORTEX M0 FACULTY COMPUTER ENGINEERING INTRUCTOR PhD. NGUYEN MINH SON Master. NGUYEN DUY MANH THI HO CHI MINH CITY, 2021 THONG TIN HOI DONG CHAM KHÓA LUẬN TOT NGHIỆP Hội đồng cham khóa luận tốt nghiệp, thành lập theo Quyết định số. của Hiệu trưởng Trường Đại học Công nghệ Thông tin.
ACKNOWLEDGEMENT First of all, we would like to express our sincere thanks to all the teachers of the University of Information Technology - Vietnam National University Ho Chi Minh City, especially the teachers of Computer Engineering, have facilitated us to learn a lot of knowledge and experience throughout the learning period. In particular , we would like to sincerely thank Dr. Nguyen Minh Son and Mr.Nguyen Duy Manh Thi have guided the group very enthusiastically throughout the course of the project, supporting and providing us with valuable and valuable knowledge so that the group can complete the topic. At the same time, we would also like to sincerely thank our friends, brothers and sisters, who have helped us find information and encourage us, to exchange and solve problems for us.
During the implementation of the thesis. Finally, we would like to thank SNST & Finger Vina for supporting us in the best possible way to complete this thesis. Despite great efforts and efforts, knowledge and experience are still limited , so the report cannot avoid many shortcomings. We are looking forward to receiving many comments and comments from teachers.
Once again , we would like to sincerely thank! Ho Chi Minh, 26 June 2021 Student 1 Student 2 Nguyen Thanh Cong Pham Quoc Huy CONTENT Chapter 1. Flow Soc design And Static Timing Analysis (STA) In Flow Soc. Flow Soc Design. _ Static Timing Analysis In Flow So.
TIMING VERIFICATION, STA CONCEPT AND PRIMETIME j/9:49)9)9/4919)001555. Dynamic timing analysis (DTA). Static Timing Analysis (S7TA).-cccc St rey § 2. Design constraints For STA.
Timing Info For STA wee eceseseseeeesescseseseseeseeesseeeseseeesenseerseaeee 9 2. Timing Checking Criteria In STA. Concepts in STA method. Prime Time IntroductiOI.
Input Gate Level Netlist (. Input Library (lib,. Input Parasitic extraction (SPEE). Output Of PrimeTime.
Make Running Environment. ARM CORTEX M0 AND TIMING VERIFICATION PRE STA WITH 1:9/009). Overview ARM CORTEX M0. Cortex-MO pTOC€SSOT.
Design Start’s Cortex-M0 processor. Overview System Design. Pre STA And Timing Verification After Step Synthesis. TIMING ENGINEERING CHANGE OTHER AND POST STA.
Timing Engineering Change Other (Timing ECO). Introduction Timing ECO oo. cece ees ceseseseeesneneaeeeeneeeseseae 48 4. Method Fix Timing.
na cố, Áo BA TT. Check Timing After ECO0I And Make Eco02. Check Timing After ECO02 And Close Timing. Result Timing ECO With PnR 'Team.-- 5-5-5 + SS£cxetsxsrerrrkree 74 Chapter 5.
CONCLUSION AND DEVELOPMENT DIRECTION. cành TH HH TT HH TH HH giết76 5.-- ¿5 S52 St S*2E9EEESE2vxkrrrrkekereree 76 LIST OF FIGURE Figure 1-1 Flow Soc (€SiET.-- 5 E121 1 1 11 1 H121 HH gi 3 Figure 2-1 STA method.- - - 5c +6 S22 2E2EEE£EEEVEk2EEEEE E111 111111111 ke 8 Figure 2-2 Example of format SPEF (Standard Parasitic Exchanging). 9 Figure 2-3 Delay of design element Example.ccccssesssseseseeseteseseseeeseseseenes 0 Figure 2-4 Setup check. „l1 Figure 2-5 Hold check.
1 Figure 2-6 Noise integrity. 2 Figure 2-7 Cross talk affection. 13 Figure 2-8 Min puÌS©. 4 Figure 2-9 Start point and End pOÏII.-- ¿+ - 5+ +5++*+*+£+£e£zx+Erxererrerterrrre 5 Figure 2-10 Type of data pat.
¿+ tt HT HH Hư 6 Figure 2-11 Clock pat. iey 7 Figure 2-12 Clock gating path.---- - 5+ 25222222 +22 7 Figure 2-13 Asynchronous path.--- - ¿525252222 S*2E‡E£xEerrkekekerrrrkrrerrree § Figure 2-14 Launch and Capture path.-- -- + ¿5-55 525+2++++svxese+zxexsxessrx 9 Figure 2-15 Primetime tools write SDC. - ¿5-5 ¿5+5 S++x+x‡exvrrkekererre 20 Figure 2-16 Input and output delayy.-- --¿- + - 5+ 5+ 5*+*+£££££e£+t+Evxexerrxzxererrx 2 Figure 2-17 Max CapaCI(AIIC€. nh Th TH HH HH Hư 23 Figure 2-18 Max transitiOn.-- 5c SE k2 T111 0101211 010101 uy 23 Figure 2-19 Input ÏNetÏiS(.
24 Figure 2-20 Content netlist (.- + k vn 25 Figure 2-21 Input LLIDraTy.-- - -- ¿2-6 S5 S*S*2*‡E#E£ES2EEEExEEEEEkEkEkrrkrrereree 26 Figure 2-22 Content in file library (11D) .-- - «¿+ 6 ‡+‡EvEk£kekEEekerkrkekerrree 27 Figure 2-23 Input COnStTaïTIL.- ¿+ - 5552 5*2EE2£#E£+E£EEEererkrkrkrkrrrrkrkrkrrrree 28 Figure 2-24 Content Constraint [ Í ]. ---¿- + ¿xxx +‡Evk+kek£kEkeeEerekekekekrkrkerrrre 29 Figure 2-25 Content Constraint [2] .- ---¿-¿- ¿+ + 5+ St +EEE‡E##kEVEEEEEkrkrkrkrrrrrrree 30 Figure 2-26 Content Constraint [3] .- -- es ¿+5 55+ S*+E+E£k£EvEkzk+kekekrrkrkekererre 31 Figure 2-27 Input SÌPEÌE. - ¿- -- xxx vn nghệ 32 Figure 2-28 Content file SIPEIE. 32 Figure 2-29 Output of PrimeTỉme.- + + +5 Sx+esxsvevxeeevseeeerrerrrrrreeerree Do) Figure 2-30 Script :run.
34 Figure 2-31 File run __ sta. 35 Figure 2-32 Script fix ŸanOUL.-- «tt Eskrrerrrrrrkskekrrkrrrererreserercre GO Figure 3-1 Functional block diagram of Cortex-MU.--- ¿5555555 5+2 37 Figure 3-2 Simplified block diagram of Cortex-MO ProcessOr.--‹--- 38 Figure 3-3 Functional block diagram of Design Start’s Cortex-M0 Processor. 39 Figure 3-4 Simplified block diagram of Design Start’s Cortex-MO Processor .39 Figure 3-5 System top level VIGW. 6 «St k1 n HH HH 40 Figure 3-6 Design after step Synthesis.
- ¿6-6-5 St ttttreeerey 42 Figure 3-7 Working flow Pre-STA. ri43 Figure 3-8 View timing path from input port to output port. 4 O+DNnA Figure 3-9 Report timing from Tool PrimeTime. Figure 3-10 Report timing big fanout causing big violation.
Figure 3-11 Ports Inout. Figure 4-1 Timing ECO flow Figure 4-2 Upsizing the driver fix transitÏOI.-- 5c <5 ++++c‡exvrrkekererrrk 50 Figure 4-3 Insert buffer decrease transition and capacitance.------‹--:-s-+ 50 Figure 4-4 Upsize cell decrease delay timing patH. ¿555 cccxssererereee 51 Figure 4-5 Adjust clock fix setup violatiOn. --- + ¿5+5++c+s+s++cxcxseerre 52 Figure 4-6 Example insert point [].-- - ¿- ¿+ + + + ++*+k+k£k£EvEkEkekekekrrkrkrkerrrek 53 Figure 4-7 Example insert point [2].
----¿--- + 5+ 5++++E+x+£e£tzkzxexererrkrkerrrre 54 Figure 4-8 Flow check timing post S”TA.- -- ¿6 + St #vEekevekekekrkrkrerree 55 Figure 4-9 Working flow Timing ECO with PnR Team .-----:55-- 56 Figure 4-10 Report max traïnSitÏOI. - - 55-55 52t SE+E2EkeErrkekEkerrrkrkrkrrrree 57 Figure 4-11 Report max CaDACI{ATIC€. 5 1t vn 58 Figure 4-12 Report S€tD. 59 Figure 4-13 Report lhOÏ.
¿E5 3191212111 112 E111 111 1 1g gu 59 Figure 4-14 Example violation hold .------ - ¿55+ ++£££+£+k+xexexerzkzkererrx 60 Figure 4-15 Check margin setup .ccccccsesessseecssssessseseeneeseeeseseseseneeeeerseasseneeeeeeee 6l Figure 4-16 Insert buffer fix hold violation .-¿-¿-¿ <5 55+ ss£+csx+zzezerersese+ 62 Figure 4-17 Margin setup after insert bufeT.------ - - 25+ 5++++£+s++erzxzxerersrx 63 Figure 4-18 Report max transition [2] .-- +5 ++c+x+xexererereeerseersererrerred 64 Figure 4-19 Report max capacitance [2] .----- + +5++++++c2x+x+xexexerrxrrerrrree 65 Figure 4-20 Report setup [2]. cesesesececscsescsesssesssseecsssesesesssesssseessesseeeasee 66 Figure 4-21 Report hold [2] .-- - ¿+ - + 55 5*2E£E+£#E£EEk£EEEEEEEEkEEEEErrkrkrkereree 66 Figure 4-22 Script file ECO0OI to Apply for PnR team.------ - -=+5<<+ 67 Figure 4-23 Report max transition after ECOO].-- ¿+ 5 + c+c+x+eececeesee 68 Figure 4-24 Report max capacitance after ECOO[.--¿- 5 + <5++++x+c+xcr+ 68 Figure 4-25 Report timing setup and hold after ECOOI.------- --+-s<+ 69 Figure 4-26 Report max transition after ECOOI [1]. 710 Figure 4-27 Report max capacitance after ECOOI [1] 70 Figure 4-28 Report timing setup and hold after ECOOI [1]. „71 Figure 4-29 Violation transition.
„71 Figure 4-30 Report timing through pin. 72 Figure 4-31 Size_cell fix tranSIfÏOH.- -- + SE k1 0101 1y 72 Figure 4-32 Report max transition after ECOO2.-- ¿2+ 55+ ssc+++z++cvesr+ 72 Figure 4-33 Report max capacitance after ECO2.- ¿+ + c+Scsxcerererereee 72 Figure 4-34 Report timing setup and hold after ECOO2.---------:-+-+ 73 Figure 4-35 Report max transition after ECO02 [1]. cere 73 Figure 4-36 Report max capacitance after ECO02 [[] .--- +5 <<<++ 73 Figure 4-37 Report timing setup and hold after ECO02 [ I].---«-+-=+ 74 LIST OF TABLE Table 3-1 Specification Of Des1gn.--¿ cece St kg Al Table 4-1 Report summary timing violation corner ff [1] 0. eee 56 Table 4-2 Report summary timing violation corner Ss [Ï].--- -«-s-s=e<«s+ 63 Table 4-3 Report summary timing violation corner ff [2] .--- -«-« se68 Table 4-4 Report summary timing violation corner ss [2].
Table 4-5 Result Timing Corner func_Ffpg_Op95v_125c_sigcmin Table 4-6 Result Timing corner func_Sspg_Op95v_125c_sigcmax. LIST OF THE ABBREVIATION ABBREVIATION FULL STA Static Timing Analysis SoC System On Chip ASIC Application Specific Integrated Circuit DTA Dynamic Timing Analysis VLSI Very Large Scale Integration PnR Place And Route WNS Worst Negative Slack TNS Total Negative Slack NVE Number Violation Endpoint SUMMARY OF THE THESIS Static Timing Analysis (STA) is one of the techniques to verify design in terms of timing. This kind of analysis doesn't depend on any data or logic inputs, applied atthe input pins. The input to an STA tool is the routed netlist, clock definitions (or clock frequency) and external environment definitions.
The STA will validate whether the design could operate at the rated clock frequency, without any timing violations. Some of the basic timing violations are setup violation and hold violation. And we will connect with other teams to solve the timing violation issues. Our mission is clean timing for design.
We will present about ARM CORTEX M0 applications and its structure. Our information, We refer some netlist file from Mr. Nguyen Tran Vinh Khang — 15520344 to get our ARM CORTEX M0 by verilog code. Introduction SOC (System On Chip) - ASoC (System-on-chip) is a microchip (IC) that integrates the components of a computer or other electronic systems.
The SoC system can include digital, analog, mixed-signal, and radio frequency (RF) function blocks. - The recent development of semiconductor technology allows us to integrate more and more components into a system on a single chip. thanks to design support software - EDA/CAD, the work of designing by drawing technical diagrams (Schematic) for designs is no more. Therefore, the design phase is significantly improved to meet the increasing requirements for speed, complexity and on-chip integration.
- SoC designs typically consume less power and cost less than multi-chip systems when compared with the same design. In addition, the single-chip system is also more stable. Applications built on the basis of single-chip systems also offer lower costs, less space occupied. Flow Soc design And Static Timing Analysis (STA) In Flow Soc 1.
Flow Soc Design Cell description coding Ỳ Logic Simulation v > Logic Synthesis + Formal Verification Ỳ Static Timing Analysis (STA) + > Physical Synthesis Ỷ Physical Verification Ỷ Static Timing Analysis (STA) Finished design Figure 1-1 Flow Soc design Soc flow consists of two design phases, Front-End and Back-End. We will interpret flow figure 1-1 as follows: e Front-End: In this phase, include the steps RTL coding, Logic simulation, Logic synthesis, formal verification and static timing analysis (Pre STA) = Every design before being implemented must have a specification that includes the goals the design needs to achieve (Power, operating frequency, temperature.) and a description of the behavior of that design. From specification and behavior description, the design will be translated into hardware language (Verilog, VHDL, System Verilog. = Next will be Logic Verification to see if the design has run correctly and functions as expected.
= If the design has guaranteed to function properly, the Logic Synthesis stage will be performed. At this stage, the design will be synthesized from RTL code to logic circuits. = Once the results from the above step are obtained, to check the synthesis logic circuit is functionally similar to the RTL design, the Formal Verification step will be performed. = Finally, the design is tested for responsiveness in time through a static timing analysis (STA).