VIETNAM NATIONAL UNIVERSITY - HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING NGUYEN VAN DUNG THESIS NGHIEN CUU, HIEN THUC VA TONG HOP ARM CORTEX-M0 32-BIT RESEARCH, IMPLEMENT AND SYNTHESIS OF THE 32-BIT ARM CORTEX-M0 ENGINEER OF COMPUTER ENGINEERING HO CHI MINH CITY, 2021 VIETNAM NATIONAL UNIVERSITY - HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING NGUYEN VAN DUNG - 17520378 THESIS NGHIEN CUU, HIEN THUC VA TONG HOP ARM CORTEX-M0 32-BIT RESEARCH, IMPLEMENT AND SYNTHESIS OF THE 32-BIT ARM CORTEX-M0 ENGINEER OF COMPUTER ENGINEERING SUPERVISOR Dr. NGUYEN MINH SON MEng. NGUYEN DUY MANH THI HO CHI MINH CITY, 2021 LIST OF DEFENSE COUNCIL MEMBERS Graduation thesis council established by Decision number 462/QD-DHCNTT dated on July 23", 2021 of Rector of the University of Information Technology. - — Chairman " — — Secretary Ql ÒÔ — Commissioner ACKNOWLEDGEMEN I want to send my sincere to all the lecturers of the VNUHCM - University of Information Technology, especially lecturers of faculty of computer engineering, has demonstrated valuable knowledge, practical experience to me during the process of learning, training at university and supported me necessary conditions to carry out this thesis.
I wish you and all the lecturer's good health and success in life. Talso would like to send my sincere thanks to Dr. Nguyen Minh Son — lecturer of the faculty of computer engineering and MEng. Nguyen Duy Manh Thi (SNST & Finger Vina Co., Ltd) who has guided and assisted me with many valuable suggestions during the process of this thesis.
Thank you for helping, motivating and providing me with professionally valuable knowledge to finish the project on time. Sincerely, thank my family and friends who are always there to encourage, support, and help me on my chosen path. Completing this thesis is the result of my huge effort and passion. Within my limited knowledge and experience, this thesis report cannot avoid mistakes.
Therefore, I am looking forward to receiving your feedback and comments.Once again, thank you very much!. Ho Chi Minh City, July 23 th 2021 Student Nguyen Van Dung TABLE OF CONTENT CHAPTER 1: INTRODUCE OF ARM 32-BIT CORTEX-M0 PROCESSOR. ARM Cortex OV€TVI€W. ARM Cortex A series (ApplicatiOn).
ARM Cortex R series (Real Time). ARM Cortex M series (MicrocontrOÏÏ€). ARM CORTTEX-MU. (HT HT HH ri4.
ARM Cortex-MŨ OV€TVICW. Block Nested Vectored Interrupt ControlÏer. Block Watchpoint Ủni(.- +: 12121 SE HH thư 0 1. Occurred issues in system [3] .- - ¿+ 6 SSEEk#kekeEEEEkg th rưy 3 CHAPTER 2: SYSTEM ON CHIP DESIGN.
sành HH TH HH HH HH rên 8 2. Specification — RTL €Oding. Static Timing Analysis. ccc cece ce eesesesesceseseseaesesseneseseseeneneee 20 2.
Design For Test.- cà" HH HH HH trên21 2. Sàn HH Hàn22 2. Placement and Optimization. Clock Tree Synthesis.
cà HH HH HH hưu 23 CHAPTER 3: SYNTHESIS AND IMPLEMENT OF ARM 32-BIT CORTEX MO PROCESSOR 24 3. RTL design woe ccc cecsesesesecseecscscsesesesesscscscsesesesssscesssssseesasenseseee 26 3. Physical technology libraries. Build the environmeiIL.
¿s5 Sx2tt2vttrtererrrrerrrrerrerrrrrrrrrrrrrrer 29 3.ìĂ Ăn HH HH HH erưên29 3. tt SH 212101112 re 33 3. Running the analyze and elaborate Comimmands. Issue step read design.
chen HH niên 37 3. Define design enVirORIN€II. Drive Characteristics for Input POFS. Defining Loads on Output POFS.
Defining Fanout Loads on Output POrts. Wire Load Model for Design. Set design constraints. __ Clock Uncertainty — Source Latency — Network Latency.
Maximum Transition Time. Group path oo. sàn HH HH nhiệt49 3. Select compile strategy.
Synthesis and optimize the design. Logic-Level Optimization.cceccecceees cece eseeesneeseseseeteneseeeseeeee 52 3. Gate-Level Optimization. cece cece cece -c+5+5+5c+ccxssercrrerrrereree 53 CHAPTER 4: ANALYZE & RESOLVE DESIGN PROBLEMS.
Updated versions of the netlist. Issue of the RTL code ARM CORTEX-MO. Issue feedback from PnR/STA/DET. Analyze the result of projects .run_env_STA_checKÌ .run_fix_timing.
CHAPTER 5: CONCLUSION & FUTURE RESEARCH. Achieved Skills nh .----c tt HH rênT7 5. Limitations and future researchh. cọ St t nh.
79 APPENDIX A — BASIC COMMANDS. co rnierrrrerrrrrrrrrrrrrrrrrrrree 80 Commands for Defining Design Rules. - ¿5-5-5 252 5£S++S£x‡£z£vzxzkexexereree 80 Commands for Defining Design Environment .--¿- - 5: 2 + 5+5 s+s+s+£++ 80 Commands for Setting Design Constraint .----¿-¿-5-5525+5+2++x+s+ses+sx+ 81 Commands for Analyzing and Resolving Design Problems.------ 82 LIST OF FIGURES Figure 1-1. Functional block diagram of Cortex-ÌMD.
Processor modes and state in Cortex-ÌMŨ. Simplified block diagram of Cortex-MO ProC€SSOF. Block diagram of Vinh Khang system design. + - + TT HH HH TH HH Hiện 12 Figure 2-1.
SOC design fÏOW. 010110 Ho rên 16 Figure 2-2. --- - ¿5< +56 S*£ESE£k#keEEEEEEEEEkErrkrkrkekrtkrrie 17 Figure 2-3.-- ¿+ + tt nghiện 19 Figure 2-4.- -- - + 6S 4 11212111111 121012111110 HH Huệ 20 Figure 2-6. Placement and Routing ÍÏOW.
Floorplan and Power Mesh. Coarse Placement and Legalization.---‹--- + + ++++++s+sece>++x+x+ses+ 22 Figure 2-9. HC HH uy 23 Figure 3-1. xxx kg HH Hiện 25 Figure 3-3.
Example RTL file. Example of a cell description in .tluplus file Figure 3-7. Layer mapping file.--¿- «5< HH reeeerrrrererrerrccee OO Figure 3-10. HH1 0 gu ờn 31 Figure 3-12.
Specifying logic lITaTi€S. --¿- - + sees Stk‡‡EvEkEEkEkekekrekekrerrrie 35 Figure 3-15. Specifying physical IÏDraries. Setup libraries for DC tOO].
The announcement has read design fpga_ tOp.c ccc ccesecsececseecseseseseseeesssessseseseneeseeeseseees 38 Figure 3-19. Schematic fpga_top by DC toOl. Commands Used to Define the Design Environment. Operating Conditions Report.
Driving cell for port A.-- - + ¿+ +5 SE**k2k‡EEEEEEEEkerrrkrrkekrtrrrie 41 Figure 3-23. Output capacitive load for port B. Output capacitive ÏOad. Commands Used to Design Constraint.
Major Design Rule Constraints .--¿-¿- 5< 252 5++++xe++£erzxsxerer+ 43 Figure 3-27. Major Design Optimization ConstrainfS. create_clock required argument. Clock waveform perIOC.--- sees cesesesesceseneaeseseesssesestsneneneseeneas 45 Figure 3-30.
Modeling Clock Sew .- + St St Hiên 46 Figure 3-32. Timing Latency — Uncertainty — Transition [Š]. Paths in the same path group. The single-cycle timing relationship of a constrained path.
Design to fpga_top Compile Strategies Figure 4-1. Notice not reading design fpga_top by DC tool. List inout ports. List big anOUI.- - - + xxx vn HT TT HH Hiện 58 Figure 4-4.
The design only uses one clock CSCCLK[0]. create_clock for design .cccceeecseecees cesses seeeseseseseesesseatseeneneseeeeesnenene 59 Figure 4-6. List ports in bus TOIm. Size cell D_FF -> Scan_ FE.
6 sàng gi 6l Figure 4-8. The clock constraint block Contains. Sumary design constraints in Ver 26.---- - - + 25+ ss+sc++x+x+xexsrree 65 Figure 4-10. Hierarchical Module post synnthe€SiS.
Schematic fpga_top post synthesis by DC tool. Compare violations per-synthesis with constraints. Quality Of RsuÌfs. Setup — hold violations for path.
Setup violations 72 path. Hold violations 15 path. esses cscs 3 k# Shin 70. Result global timing synthesis ARM Cortex MŨ.
Setup violations 19 patH. -- -- xxx ngư 71 Figure 4-20 - No hold Violation. Schematic fpga_top post-synthesis by DC tool. Show partial gate-level netlist Íbga_tOD.
Show partial constraints netÏiSf. -- ¿55555 2+2++xseexererrxererrre 77 LIST OF TABLES Table 1-1. Summary of processor mode and stack use Options. NVIC registers, each with a width of 32 bits.- cscs eseseeesscecscsesesesesesecscsessssseeaneeeseneeseaeee 9 Table 1-4.
-‹- - nàn HH gi 10 Table 1-6. Bus system €ÏOCKS. Scripts used for S€(UD. 6 + 11x v9 HT Hiến 32 Table 3-2.
Output file post synthes1S.----- - +: 522SS2S*2E‡x2EE*EE2EEEE 2111k cxee 33 Table 3-4. Design Rule Command and Object Summary. Design Optimization Command and Object Summary. Design Specifications for Design fpga_top.
Updated versions of the netlist ARM 32-bit Cortex M0. - 6 1 1t t vn HT TH Hư 56 Table 5-1. Design constraints specification for design fpga_top. The comparison results between pre-synthesis and post-synthesis.
T5 ABBREVIATIONS ARM Acorn RISC Machine ASIC Application-Specific Integrated Circuit CAD Computer Aided Design CMSDK Cortex-M System Design Kit CMSIS Cortex Microcontroller Software Interface Standard DFF D-Flipflop ECO Engineering Change Order EDA Electronic design automation FA Full Adder FF Flipflop FPGA Field-programmable gate array GPIO General Purpose Input Output Ic Integrated circuit IP Intellectual Property ITCM Instruction Tightly Coupled Memory LAB Logic Array Block LE Logic Element LUT Look-Up Table MTI Model Technology Incorporated NVIC Nested Vectored Interrupt Controller OS Operation System RAM Random Access Memory ROM Read-Only Memory RISC Reduced Instructions Set Computer RTL Register Transfer Level SDC Synopsys Design Constraint SoC System on Chip UART General Asynchronous Receiver Transmitter VLSI Very-Large-Scale Integration THESIS ABSTRACT ARM microcontroller architecture (short for original Acorn RISC Machine) is a 32-bit RISC type of microprocessor architecture widely used in embedded designs. It was developed for the first time in a project by Acorn Computer Company. Due to their energy- saving characteristics, ARM CPUs dominate in mobile electronics, for which low power dissipation is a key design goal. ARM CORTEX MO chip is researched and developed and is widely used in measurement and control.
In particular, ARM chips are researched and applied to produce handheld devices such as phones, cameras, and devices that require high processing speed, such as televisions, equipment to process digital signals. This thesis aims to synthesize the RTL code of 32-bit ARM Cortex-M0 with SoC design flow. This RTL code is based on a relatively simple implementation on FPGA platforms using standard hardware description and software programming languages by Nguyen Tran Vinh Khang — 15520344. Design block includes basic DMA, AHB bus system, APB bus system, Arm Cortex-M0 architecture; wake-up interrupts feature, serial wire debug and JTAG debugging, AHB-GPIO, APB-UART, APB-SPI, APB-I2S, APB- I2C, APB-SCC, AHB-SSRAM, AHB-SDRAM, boot processing, interrupt processing.
A system on chip (SoC) is an integrated circuit (also known as a "chip") that integrates the most important components of a computer or other electronic system. More tightly integrated computer system designs improve performance and reduce power consumption, as well as semiconductor, die area than multi-chip designs with equivalent functionality. SoC designs use hundreds of millions or billions of transistors, so it takes a lot of money and time to design. Therefore, the design implementation process should be divided into different stages that require high productivity for each engineer.
SoC design includes main steps: RTL Description Coding, Logic Simulation, RTL Synthesis, Formality Verification, Static Timing Analysis and Physical Design. RTL Synthesis step is to transfer from Register Transfer Level — RTL (high-level description) to synthesized and optimized gate-level Netlist (low-level description). I use the Design Compiler tool to synthesize 32-bit Cortex-M0 RTL code and combine it with related libraries such as Logic libraries (cell library, .), Physical libraries (TLUplus, 32nm technology file, .) and design constraints. After synthesis, we’ll optimize the 1 design to meet the requirement of performance, area, power.
The ARM 32-bit Cortex-M0 Gate-level Netlist is generated after optimization and provided for other design steps. The thesis of this report is divided into five chapters with the following main contents: Chay pter 1: INTRODUCE OF ARM 32-BIT CORTEX-M0 PROCESSOR Chay pter 2: SYSTEM ON CHIP DESIGN Cha) pter 3: SYNTHESIS AND IMPLEMENT OF ARM 32-BIT CORTEX-M0 PROCESSOR Cha; pter 4: ANALYZE & RESOLVE DESIGN PROBLEMS Chay pter 5: CONCLUSION & FUTURE RESEARCH CHAPTER1: INTRODUCE OF ARM 32-BIT CORTEX-M0 PROCESSOR 11. ARM Cortex overview ARM Cortex processors are divided into three lines, denoted by the characters after the Cortex name: A (Application) and R (Real-time). The ARM Cortex is a different version from the ARM versions typically denoted by ARM.
ARM Cortex does not have a certain speed of operation or peripheral system; depending on the hardware manufacturer will design different peripheral systems. However, they all use the same ARM Cortex core and programming and tracking. Hardware updates must comply with CMSIS standards. From 1994 to 2015, Cortex-A core sets developed from AO to A18; Cortex R developed from RO to R7; Cortex M developed from MO to M7 [1].
ARM Cortex A series (Application) The ARM Cortex-A processor is a high-performance processor that offers a wide range of solutions for devices performing complex computing tasks, such as hosting a rich operating system (OS) platform and supports many software applications.