VIETNAM NATIONAL UNIVERSITY HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING NGUYEN LE NHAT HAO VU THI HONG NHUNG GRADUATE THESIS PLACE AND ROUTE IMPLEMENTATION OF THE 32-BIT ARM CORTEX-M0 ENGINEER OF COMPUTER ENGINEERING HO CHI MINH CITY, 2021 VIETNAM NATIONAL UNIVERSITY HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING NGUYEN LE NHAT HAO- 17520447 VU THI HONG NHUNG- 17520863 GRADUATE THESIS PLACE AND ROUTE IMPLEMENTATION OF THE 32-BIT ARM CORTEX-M0 ENGINEER OF COMPUTER ENGINEERING INSTRUCTORS PhD. NGUYEN MINH SON MSc. NGUYEN DUY MANH THI HO CHI MINH CITY, 2021 INFORMATION OF THE GRADUATE THESES ASSESSMENT COUNCIL The graduate theses assessment council, established under Decision No 462/QD-DHCNTT on 23" July 2021 of the rector of University of Information Technology. ACKNOWLEDGEMENTS We would like to express our sincere gratitude to the lecturers at University of Information Technology for letting us to be great students here.
We would also like to thank SNST & Finger vina company for giving us the opportunity to do this honor thesis. We are extremely thankful to my faculty guide Mr. Nguyen Minh Son for his valuable guidance and support for the completion of this project. We also acknowledge with our gratitude to Mr.
Nguyen Duy Manh Thi, Mr. Ngo Thanh Sang from SNST & Finger vina company to have technical supports so that we could finish out project. Finally, we want to show our regards to all our colleagues who directly or indirectly helped us to complete this thesis report. Ho Chi Minh city,.
July 2021 Students Nguyen Le Nhat Hao Vu Thi Hong Nhung TABLE OF CONTENTS Chapter 1. INTRODUCTION TO CHIP DESIGN FLOW. SoC design ÍÏOW. án TH HH HH HH TH gi 2 Chapter 2.
BACK-END DESIGN FLOW USING SYNOPSYS TOOL. Introduction of IC Compiler II tool. Place and route design flow using IC Compiler II tool. Place and route design flow v.
Libraries preparation and design inputs. Overview of Input setup for ICC2. Overview of FIOOrplAN $Sf4§€. 55555 S25+5++++x+sv+e+cs++xscex Il 2.
Basic terminologies before FÏOOFDÏAH. SE HH tiệt 15 2. Overview of powerplan Sf€. Powe rplan Structure.
St 3E E SE ng ri J8 2. Checks after pOV€TÏ4H. Overview Of PIACEMENE SÍ(48€. PoWer COHC€BIS.
Analyze the design after DÏAC€IH€HI. Clock tree synthesis. Overview of Clock tree SYNtheSis. Clock Tree Synthesis steps.
Analyze the design after CTÁ. Overview Of TOHÍ€. Analyze the design after ÑOufe. ARM CORTEX-M0 OVERVIEW & SPECIFICATION.
nh HH HH HH tr ườc 38 3.11 Cortex-MO DFOC€SSOF'. DesignStart’s Cortex-MO prOC€SSOF. DesignStart’s System đ€SỈETH. ASIC post-synthesis design stTUC{UT€.
ASIC physical design specification Chapter 4. ARM CORTEX-M0 IMPLEMENTATION RESULT. ARM Cortex MO inpUIS. Read design input St€D.
Power COMIN CF€([ÏOHN. 2S St S*E‡EEEk‡‡EeEekererrkekrkreree 48 4. POWF TINGS CTF€[ÏOHH. kề TT nghiệt 50 4.4, Power straps creation.
Power rails CT€(fÏOHH. Check results after powerplan.” HH HH run55 4. SE E3 BE iệt 37 4. Clock tree synthesis S(€D.
ng HH gi 61 4. CLOCK SEGUC Ib ey see OT nan TER vss co. LH HH HH 1 ke 61 4. Clock tree synthesis results.
Check DRC, LVS using ICC2 to. Report utilization At FOHR€. Analyzing timing quality & cell COUNT At roHfe. Analyzing cell type & power usage report Al TOULE.
STA timing Engineering change order (ECO). ECO WOrking ƒÏOWV. CONCLUSION & FUTURE WORK .- 6+ ket HT tên78 5. Future work LIST OF FIGURES Figure 1.
1 GUI interface of IC Compiler II. ¿5-5 25+ 5s5s+<+£+£sze>s+ezeexs 3 Figure 2. 2 IC Compiler II place and route ÏOAW. 3 ICC2 input setup OV€TVICW.
Sàn HH HH. 4 Layer definition in technology file. 5 Unit tile definition exaimpÌe. 6 NDM reference library files.
7 Example content in. 8 Example content in .------- - +52 522<+++c+cvs+ezxrrererrxee 9 Figure 2. 9 Example content in. 0 Example content in.
1 Example content in. 3 Site row im đ€SigT. 4 Types of core Shape .-- 1S 1k 2 HH HH Hi. 15 Die and core boundary in deSign.----- - + ¿5-55 ssc>+z++c+eex+ 5 Figure 2.
6 Macros placement example. 7 Tap cell placement example .---- 5-5252 5+5++c+s+sec+>xsxsxrree 6 Figure 2. 18 Boundary cell placement exampÌe. 19 Core rings and Macro rÏTS.---- +5: 52525 St +tzEexeverertresrerre 8 Figure 2.
20 Power meshes Structure. 21 Power rails SITUCTUTE. 5 S11 1 SH it 9 Figure 2. 23 Types of timing pa(Ï.-- ‹- «th Hit 23 Figure 2.
24 Elements of timing cheCK. 25 Scemari0s CT€ALÏON. c5 c2 tt th ren 26 Figure 2. 26 Before and after CTS example.
27 NDR rules example. 28 Metal layers exaImpÏe.-- ccc -<< +2 1E 1111 9 vn HH, 33 Figure 2. 29 VIAS example nh. 30 Multi cut vias example .-- 4 5 5 1E ng ng ưy 34 Figure 2.
34 Global routing expÌanafIOII.- --- 5 5< vn ng ngư 35 Figure 2. 35 Track assignment eXaImpÌÏe.-- 5 5 2+ 1v ng ngư 36 Figure 2. 36 How detail routing WOTKS. -- - cv HH Hư, 36 Figure 3.
1 Functional block diagram of Cortex-ÌM. 2 Simplified block diagram of Cortex-ÌMŨ. 3 Functional block diagram of DesignStart’s Cortex-MO Processot. 4 Simplified block diagram of DesignStart’s Cortex-MO Processot.
5 Example system top level VieW. 6 Design view after ASIC Synthesis 0. cece eeeesecesecesesesesseeeeeeseenes 42 Figure 4. 1 Design input all VersiONns.
2 Design netlist CONtENE. ec eecceeeeceteceeecesceceseeceseeesaeeeeeceaeeseaeessaeeeaees 44 Figure 4. 3 Design SDC content. 2G 2 2211321133 1113 11 9 11 81 1H ng ngư45 Figure 4.
4 Read design ÍÏOW .- HH HH HT TT HH Hàn HH hiệp 45 Figure 4. 6 Operating ScenariO SCtUP SCTIR.- 5 11x kg key 46 Figure 4.- - c1 TH HH HH kg krry 47 Figure 4. 8 Script for placing POTts. 10 Power domain creation ÍÏOW.
11 Power domain creation SCTIPt. --- 5 5 + + ve reereerre 49 Figure 4. 12 Ring creation ÍÏOW.-- - «ch HH ng HH vờ 50 Figure 4. 13 Script to vi 0020107.
14 Power ring eXpÏa'nafIO.-- <5 + 1313311131189 1 E11 E11 vn rry 51 Figure 4. 15 M9 horizontal/MS vertical ring. 16 Straps creation ÍÏOW/.-- -- HH HH HH rưy 51 Figure 4. 17 Script to create DOW€T STADS.
18 Power strap explanation. 19 M7 horizontal/M2 vertical straps. 20 Standard cells rail creation ÍÏOW.- cv ni, 53 Figure 4. 21 Standard cell rails SCript.
22 Standard cell rail explanation. eee ee sseeseeseeseeeeneeseeeceeseeceeeeeeeaes 53 Figure 4. 24 Checks result at pOWerpDÏ4T. s1 ng ng ng cư, 54 Figure 4.
25 Design logical hierarchy. 26 CMSDK_mcu_system cell placemen(. 27 Fpga_apb_subsystem cell placermeIi(.-- «- «+ es£+s£+sc+se+se+sxr+ 56 Figure 4. 28 Remaining sub modules cell placement.
29 Congestion map at pÏaC€IN€TI.-- 5 5 25 2+ E++sEE+seeEseeerseeeese 57 Figure 4. 30 Cell density map at pÏaC€Tm€n(. 31 Pin density map at pÏaC€I€TI. 32 Utilization at pÏaC€Tm€TI(.
33 Report timing quality at placement. 34 Report cells usage at pÏaC€Im€TI(. ee <6 + + ***E*kEskreerekree 60 Figure 4. 35 Report power usage at DÏaC€IT€TIE.
36 Clock structure at CTS. co HH HH ưy 61 Figure 4. 37 Latency report - corner ff_0pO5v_ 125C.- -c kcstk* + se, 62 Figure 4. 38 Latency report - corner ss_p95v_ 125C.
39 Latency path report to clock endpOITIE. 40 Latency path after cell S1Z1NE. 41 Final clock latency - corner ss_p95v125C. 42 Utilization at CTTS.
s9 gTHggg Hgnghrưn 65 Figure 4. 43 Report timing quality at C'TS. 44 Report cells usage at CÏTTS.- cành HH nghiệt 66 Figure 4. 45 Report power usage at CTTS.- - LH HH HH nh 67 Figure 4.
46 Check LVS report at TOU. HH ng Hy67 Figure 4. 47 Check DRC report at route. G5 vn HH ng 68 Figure 4.
48 Report utilization at TOUIV€.--- - c + 113199 1v HH ng re 68 Figure 4. 49 Report timing quality at TOUC.- óc s1 1v ng ng rn69 Figure 4. 50 Report cell usage at route. 51 Report power usage at TOU .-- Ác 5 1 ng gệt 70 Figure 4.
53 Timing report before ECO Ï,.-- 6 s11 ng rey 72 Figure 4. 54 Max trans report before ECO 1. 55 Max cap report before ECO 1. 56 Script to TUN ECO 100.
57 Timing report before ECO 2.- --- 55 + kg nh ng 74 Figure 4. 58 Max trans report before ECO 2 .- -- -c 2< x9 ng re 74 Figure 4. 59 Max cap report before ECO 2. -- c1 2x11 v9 vn rey 75 Figure 4.
60 Script to run ECO 2. 2c c 1 23 11v 991119 vn HH ngư, 75 Figure 4. 61 Final timing after ECO 22. 62 Final max tran/cap result after ECO 2.- -- «+ sccsec+seesessessrs 75 Figure 4.
63 Design final power COnSUINPẨIOH. 64 ARM Cortex MO ÏayOUI. G11 kg krưy 77 LIST OF TABLES Table 3.1 Items in DesignStart’s example SySf€im. ¿655cc Sc+csxseevrerersee Al Table 3.2 Design specification at Place and route .2 Cell count by type between design input and placemenI.3 Cell count by type between Placement and CTS.4 Cell count by type between CTS and Route.5 Cell count difference from Route to ECO2 .6 ECO summary T€SUÏ(L.- - + + 5S SkEvEvEEEeEekekrkrerrrekeerkrkrkrkrerrre T7 LIST OF ABBREVIATIONS CTS Clock Tree Synthesis DRC Design Rule Check ECO Engineering Change Order LVS Layout Versus Schematic PNR Place and Route PG Power Ground QoR Quality of Result SoC System on Chip STA Static Timing Analysis THESIS SUMMARY ARM Cortex-M is a family of 32-bit RISC ARM processor.
These cores are optimized for low-cost & energy saving microcontrollers. In particular, the Cortex- MO core is optimized for small silicon die size and used in the chips with the lowest price. There were many topics focusing on research, design, simulate and implement ARM Cortex-M0 on FPGA. For the topic this time, the team decided to implement ASIC physical design base on the Netlist which was completely designed and simulated on FPGA of the previous thesis.
The main goal of this thesis is to implement Place & Route of the ARM Cortex-M0 from gate-level netlist to GDSII file. We implement PnR flow following these steps: Floorplan, Powerplan, Placement, Clock Tree Synthesis, Routing using automatic PnR tool and timing Engineering Change Order (ECO) using timing sign- off tool. We have four team working on it: Synsthesis, Design for Testability (DFT), Static Timing Analysis (STA), Place and Route (PnR). For the first step, we (PnR) build a working environment to run the design.
The second step, we receive synthesized netlist, DFT netlist to test the design and give feedback to Synthesis, STA and DFT team about timing and scan chain issues. Finally, we officially implement final PnR flow, co-operate with STA team using timing sign-off tool to verify & fix timing violations of the design. In this report, we mainly discuss about: e An overview of chip design flow: logic design and physical design (Front-End and Back-End). e Basic steps in Back-End section used to implement the design: floorplan, powerplan, placement, clock tree synthesis, routing.
e Implementation result of ARM Cortex-M0 netlist using auto PnR tool. INTRODUCTION TO CHIP DESIGN FLOW 1. Introduction System on chip (SoC) is the integration of the entire system into a chip. SoC have become one of the most important branches of the semiconductor industry in recent years, allowing designs with up to millions of logic gates of integration level.
The SoC design process consists of two design phases: Front-End design phase and Back-End design phase. The Front-End design phase does the logical construction of design such as coding, simulation, setting constraints, timing analysis, etc. The Back-End design phase converts the connection between logical cells in the Front-End design phase into the connection between physical cells and actual nets. SoC design flow The full flow of SoC design associate with description is shown in figure 1.
Understanding of design purposes.