MINISTRY OF EDUCATION AND TRAINING HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION GRADUATION THESIS COMPUTER ENGINEERING TECHNOLOGY VERIFICATION FOR 5-STAGE PIPELINED RISC-V RV32I USING UVM-BASED PLATFORM INSTRUCTOR: PHAM VAN KHOA, PhD. STUDENT: TRAN VAN DU DANG NGUYEN BAO LAM SKL014344 Ho Chi Minh City, June 2024 HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION FACULTY OF INTERNATIONAL EDUCATION GRADUATION PROJECT VERIFICATION FOR 5-STAGE PIPELINED RISC-V RV32I USING UVM-BASED PLATFORM TRAN VAN DU Student ID: 18119012 DANG NGUYEN BAO LAM Student ID: 19161070 Major: COMPUTER ENGINEERING Advisor: PHAM VAN KHOA, PhD. Ho Chi Minh City, June 2024 THE SOCIALIST REPUBLIC OF VIETNAM Independence – Freedom– Happiness -------- Ho Chi Minh City, June 24, 2024 GRADUATION PROJECT ASSIGNMENT Student name: TRAN VAN DU Student ID: 18119012 Student name: DANG NGUYEN BAO LAM Student ID: 19161070 Major: COMPUTER ENGINEERING TECHNOLOGY Advisor: Pham Van Khoa Phone number: _________________ Date of assignment: _____________________ Date of submission: _____________ 1. Project title: VERIFICATION FOR 5-STAGE PIPELINED RISC-V RV321 USING UVM BASED PLATFORM 2.
Initial materials provided by the advisor: ___________________________________ 3. Content of the project: Build a UVM test bench environment to test and verify functionality for the basic RISC-V RV32I architecture. Final product: Create testcases and run simulations on the UVM testbench environment to test the functionality of the RV32I RTL design. CHAIR OF THE PROGRAM ADVISOR (Sign with full name) (Sign with full name) i THE SOCIALIST REPUBLIC OF VIETNAM Independence – Freedom– Happiness -------- Ho Chi Minh City, June 24, 2024 ADVISOR’S EVALUATION SHEET Student name: TRAN VAN DU Student ID: 18119012 Student name: DANG NGUYEN BAO LAM Student ID: 19161070 Major: COMPUTER ENGINEERING TECHNOLOGY Project title: VERIFICATION FOR 5-STAGE PIPELINED RISC-V RV321 USING UVM BASED PLATFORM Name of Advisor: Pham Van Khoa EVALUATION 1.
Content and workload of the project ………………………………………………………………………………………………. Approval for oral defense? (Approved or denied) ………………………………………………………………………………………………. Overall evaluation: (Excellent, Good, Fair, Poor) Good 6. (in words: ………………) Ho Chi Minh City, month date, 2024 ADVISOR (Sign with full name) ii THE SOCIALIST REPUBLIC OF VIETNAM Independence – Freedom– Happiness -------- Ho Chi Minh City, July 2, 2024 PRE-DEFENSE EVALUATION SHEET Student name: TRAN VAN DU Student ID: 18119012 Student name: DANG NGUYEN BAO LAM Student ID: 19161070 Major: COMPUTER ENGINEERING TECHNOLOGY Project title: VERIFICATION FOR 5-STAGE PIPELINED RISC-V RV321 USING UVM BASED PLATFORM Name of Reviewer: Vo Minh Huan EVALUATION 1.
Content and workload of the project Thesis applies UVM testbench technique in the testing and verification process for RV32I design. Then, the RTL design and UVM testbench will be evaluated and analyzed. Strengths: The UVM testbench technique is an industry standard test method for verifying the digital IC circuits. Authors has analyzed this technique very clear and apply it to verify some blocks of RISC-V.
RISC-V is analyzed and verified by using UVM technique. Weaknesses: Authors should analyze more detail in blocks of 5-stage pipelined RISC-V. Behavior simulation should be included in thesis to verify the functionality of RISC-V. Approval for oral defense? (Approved or denied) Approved 5.
Overall evaluation: (Excellent, Good, Fair, Poor) Good 6.2/10 (in words: Eight point two) Ho Chi Minh City, July 2, 2024 REVIEWER (Sign with full name) Vo Minh Huan iii THE SOCIALIST REPUBLIC OF VIETNAM Independence – Freedom– Happiness -------- HoChiMinh City, July 1 st , 2024 PRE-DEFENSE EVALUATION SHEET Student name: TRAN VAN DU Student ID: 18119012 Student name: DANG NGUYEN BAO LAM Student ID: 19161070 Major: COMPUTER ENGINEERING TECHNOLOGY Project title: VERIFICATION FOR 5-STAGE PIPELINED RISC-V RV321 USING UVM BASED PLATFORM Name of Reviewer: LE MINH THANH, M. Content and workload of the project - Including verification of the 5-stage pipelined RISC-V RV321 architecture using the UVM-based platform. Each sub-block is fully testbenched with a specific testcase. Strengths: - Explanation of figures in the thesis is clear and mapping to the requirements.
Weaknesses: - The similarity rate of 22%. - All numbered figures are incorrect. Approval for oral defense? (Approved or denied) - Approved. Overall evaluation: (Excellent, Good, Fair, Poor) - Good.0 (in words: Eight) HoChiMinh City, July 1 st , 2024 REVIEWER Le Minh Thanh iv DISCLAIMER We hereby declare that this thesis, titled "VERIFICATION FOR 5-STAGE PIPELINED RISC-V RV321 USING UVM-BASED PLATFORM", represents our original work conducted under the guidance of Dr.
Pham Van Khoa. The simulations, study findings, and conclusions presented in this thesis are accurate to the best of our knowledge and have not been replicated from any other sources. We have meticulously cited and referenced all sources used in the preparation of this thesis. We acknowledge the contributions of others and take full responsibility for any errors or omissions.
This thesis is submitted in partial fulfillment of the requirements for the degree of Bachelor at Ho Chi Minh University of Technology and Education. We affirm that this work adheres to the academic integrity standards set forth by Faculty of International Education, and Ho Chi Minh University of Technology and Education. We understand the consequences of plagiarism and academic dishonesty, and we pledge that this thesis represents our own independent work. Student TRAN VAN DU DANG NGUYEN BAO LAM v ACKNOWLEDGEMENTS First and foremost, we would like to thank the Faculty of International Education and the School Board of the Ho Chi Minh City University of Technology and Education for providing the right environment for me to pursue my project.
Furthermore, we would like to express our heartfelt appreciation to the department's head, Ph. Pham Van Khoa, who constantly monitors the learning environment and supports and develops growth opportunities for each student generation. Finally, a lack of experience and sluggish implementation prevent us from avoiding mistakes. Your feedback and suggestions are appreciated as we continue to improve this topic.
Regards, and many thanks for your support. Student TRAN VAN DU DANG NGUYEN BAO LAM vi TABLE OF CONTENTS CHAPTER 1: INTRODUCTION .5 Object and the scope of the study .15 CHAPTER 2: LITERATURE REVIEW .1 RISC-V 32 Instruction Set Architecture .1 RV32I Instruction Formats .2 RV32I Encoding Variants .3 RV32I Integer Register-Immediate Instructions .4 RV32I Integer Register-Register Operations .5 RV32I NOP Instruction .6 RV32I Unconditional Jumps .7 RV32I Conditional Branches.8 RV32I Load and Store Instructions .2 Universal Verification Methodology .1 UVM Testbench Architecture .2 UVM Component Class .1 UVM testbench top.3 UVM Transaction Base Class.1 UVM sequence item .1 The Program Counter module .2 The Instruction Memory module .3 The Register File module .4 The Arithmetic Logic Unit module .5 The ALU Control module .6 The Control Unit module.7 The Data Memory module.8 The Immediate Generation module .9 The Immediate Address module .3 ASM simulation testcase .3 RV32I UVM component implementation .9 RV32I testbench top .4 RV32I instruction code generation .5 RV32I reference model impletation .1 Program counter reference model.2 Immediate memory reference model .3 Register file reference model .4 Control unit reference model .5 Immediate generation reference model .6 ALU control reference model .7 Data memory reference model .6 DUT-Testbench Connections.1 Design error detection. CONCLUSION AND FUTURE WORK .90 ix LIST OF FIGURES Figure 1: RISC-V base unprivileged integer register state.17 Figure 2: RV32I formats.18 Figure 3: RV32I formats with immediate variants.19 Figure 4: RV32I type of immediate .19 Figure 5: I-type Basic instructions .20 Figure 6: I-type Shift instructions.21 Figure 7: U-type Basic instructions .21 Figure 8: R-type Basic instructions .22 Figure 9: I-type NOP instruction .22 Figure 10: J-type JAL instruction .23 Figure 11: J-type JALR instruction .23 Figure 12: B-type Branch instructions .24 Figure 13: I-type LOAD instruction .25 Figure 14: S-type STORE instruction .25 Figure 15: RV32I processor block diagram(Patterson and Hennessy, 2017).26 Figure 16: UVM Testbench Architecture .28 Figure 17: UVM hierarchy .29 Figure 18: UVM component hierarchy .29 Figure 19: UVM testbench top in UVM .31 Figure 20: UVM testbench top hierarchy .31 Figure 21: UVM test in UVM .33 Figure 22: UVM test hierarchy .34 Figure 23: UVM env in UVM .35 Figure 24: UVM env hierarchy .35 Figure 25: UVM agent in UVM .36 Figure 26: UVM agent hierarchy .37 Figure 27: UVM driver in UVM .38 Figure 28: UVM driver hierarchy .39 Figure 29: UVM monitor in UVM .40 Figure 30: UVM monitor hierarchy .40 Figure 31: UVM scoreboard in UVM .41 Figure 32: UVM scoreboard hierarchy .42 Figure 33: UVM transaction hierarchy .42 Figure 34: UVM sequence in UVM .43 Figure 35: UVM phase step.44 Figure 36: RV32I Program Counter block diagram (Patterson and Hennessy, 2017) .45 Figure 37: RV32I Instruction Memory block diagram(Patterson and Hennessy, 2017) .46 Figure 38: RV32I Instruction Memory block diagram(Patterson and Hennessy, 2017) .47 Figure 39: RV32I Instruction Memory block diagram (Patterson and Hennessy, 2017) .47 Figure 40: RV32I Instruction Memory block diagram (Patterson and Hennessy, 2017) .48 Figure 41: RV32I Data Memory block diagram (Patterson and Hennessy, 2017).50 Figure 42: RV32I Immediate Generation block diagram(Patterson and Hennessy, 2017) .51 Figure 43: Pipelining breaks the critical path segregating the combo logic and adding registers in between classic RISC-V stages .52 Figure 44: Multiple Instructions executed with Pipeline Implementation .53 Figure 45: the concept of separating the datapath flow into several stages .53 Figure 46: Pipelined Datapath with Control Elements integrated .54 Figure 47: RV32I UVM Testbench Architecture .55 Figure 48: UVM flow chart .56 Figure 49: Code of uvm sequence item .58 x Figure 50: Code random test in uvm sequence item .59 Figure 51: RV32I UVM hierarchy .60 Figure 52: Sequence flow .60 Figure 53: RV32I_driver code .61 Figure 54: RV32I_driver code .62 Figure 55: RV32I_monitor code .62 Figure 56: RV32I_agent code .63 Figure 57: RV32I_env code .64 Figure 58: RV32I_test code .65 Figure 59: RV32I interface code .67 Figure 60: RV32I scoreboard code example 1 .68 Figure 61: RV32I scoreboard code example 2 .69 Figure 62: RV32I testbench code .70 Figure 63: RV32I sequence item code .71 Figure 64: Program counter ref_model .72 Figure 65: Immediate memory reference model .73 Figure 66: Register file reference model .74 Figure 67: Control unit reference model .75 Figure 68: Immediate generation reference model.76 Figure 69: ALU control reference model .77 Figure 70: Data memory reference model .78 Figure 71: RV32I_UVM connect diagram .80 Figure 72: RV32I build phase connection .80 Figure 73: Inject error into code DUT.81 Figure 74: UVM error message .81 Figure 75: UVM no error message .82 Figure 76: Waveform for single instruction .82 Figure 77: Order of giving 3 consecutive instructions .83 Figure 78: Waveform for 3 consecutive instructions .83 Figure 79: Random test code generation .85 Figure 80: Random test UVM message .86 Figure 81: Random test waveform .87 xi LIST OF TABLE Table 1 RV32_interface table .67 xii LIST OF ABBREVIATION ALU Arithmetic Logic Unit AND Operator AND ANDI Immediate AND Instruction ARM Advanced RISC Machine BGE Instruction Branch if greater than or equal BGEU Instruction Branch if greater than or equal unsigned BGT Instruction Branch if greater than BGTU Instruction Branch if greater than unsigned BLE Instruction Branch if less than or equal BLEU Instruction Branch if less than or equal unsigned BLT Instruction Branch if less than BLTU Instruction Branch if less than unsigned DUT Design Under Test NOP No Operation NOT Operator NOT OR Operator OR ORI Immediate OR Instruction RAM Random Access Memory RISC-V Reduced Instruction Set Computing fifth version SH Instruction Store Halfword SLL Instruction Shift left logical SRAI Instruction Shift Right Algebraic Word Immediate SRL Instruction Shift Right Logical SRLI Instruction Shift Right Logical Immediate SW Instruction Store Word UVM Universal Verification Methodology XOR Operator XOR xiii CHAPTER 1: INTRODUCTION 1.1 Introduction Nowadays, microprocessors and embedded systems are becoming increasingly widespread and diverse as a result of rapid technological development, and they play a significant part in most modern electronic products. Microprocessors are found not only in personal computers and servers, but also in smaller devices such as smartphones, IoT (Internet of Things) devices, smart home appliances, and many more applications.
RISC-V, an open and extensible instruction set architecture (ISA), has captured the attention of both the scientific community and industry throughout this period of development.