VIETNAM NATIONAL UNIVERSITY - HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING LE NGUYEN HOANG THIEN W RESEARCH DESIGN RISC-V WITH MULTITHREADING MICRO- ARCHITECTURE NGHIÊN CUU THIET KE BỘ VI XỬ LÝ RISC-V THEO VI KIÊN TRÚC MULTITHREAD BACHELOR OF COMPUTER ENGINEERING IN COMPUTER ENGINEERING HO CHI MINH, 2021 VIETNAM NATIONAL UNIVERSITY - HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING LE NGUYEN HOANG THIEN Z CAPSTONE PROJECT RESEARCH DESIGN RISC-V WITH MULTITHREADING MICRO- ARCHITECTURE NGHIÊN CUU THIET KE BỘ VI XỬ LY RISC-V THEO VI KIÊN TRÚC MULTITHREAD BACHELOR OF COMPUTER ENGINEERING IN COMPUTER ENGINEERING SUPERVISOR M.ENG HO NGOC DIEM HO CHI MINH, 2021 PROTECTION COUNCIL OF THE CAPSTONE PROJECT Defense committee of the capstone project, established under Decision No. 462/QD- DHCNTT dated July 23, 2021 of Rector of the University of Information Technology. Le eee eee e eee eee eee eee eerie — Chairman. Bo eee cece e eee eee e cence eect eee eete eee eeeaeenes — Commissioner ACKNOWLEDGMENT Nowadays, in the fast-paced life, hardware technology, especially processor, is more complicated and faster than ever before.
This development can handle some problems at the hardware level, which is faster and more optimizer than the software level. However, in Viet Nam, we can not find any piece of papers related to advanced processors. So, with all of my knowledge about IC design and hardware, we are going to implement some modern techniques and apply them to build a RISC-V core. This thesis is believed to be useful for those who want to understand the RISC-V core and some pipelined techniques.
This thesis can not complete without support from many ones. Firstly, I would like to thanks all lectures and staffs at the University of Information Technology, especially the Faculty of Computer Engineering, who try their best to give us a useful solid foundation of knowledge. Secondly, who also appreciate M. Eng Hé Ngoc Diém and Eng.
Tran Dai Duong, who has provided valuable advice and brightly guidance throughout the research process. Once again, thank you all for your unwavering support. VIETNAM NATIONAL UNIVERSITY HCMC THE SOCIALIST REPUBLIC OF UNIVERSITY OF INFORMATION VIETNAM TECHNOLOGY Independence - Freedom - Happiness OUTLINE DETAILS VIETNAMESE NAME: NGHIÊN CỨU THIET KE BO VI XỬ LÝ RISC-V THEO VI KIÊN TRÚC MULTITHREAD ENGLISH NAME: RESEARCH DESIGN RISC-V WITH MULTITHREADING MICRO-ARCHITECTURE. Ho Ngoc Diem — Univerity of Information Technology.
Start day — End day: From 08/03/2021 to 25/06/2021 Student: Le Nguyen Hoang Thien - 17521075 Content Overview: — RISC-Vis anopen standard instruction set architecture(ISA) based on established reduced instruction set computer (RISC) principles. Unlike most other ISA designs, the RISC-V ISA is open source licenses and free to access. ii — Because of the RISC-V instruction set architecture's advantages, nowadays, many technology companies, such as Alibaba Group or NVIDIA, are developing their RISC-V CPU or SoC and release their products soon. — Documents define RISC-V, just published in 2019 by RISC-V International, permit unrestricted use for software and hardware design.
That why is we cannot find any papers about RISC-V multithreading architecture by Vietnamese. Besides, very few released research pieces about the RISC-V processor worldwide, the RISC-V processor enhancing by multithreading techniques is rarer. Related Work: — About multithread: + In 1967, IBM introduced OS/360 Multiprogramming with a Variable Number of Task (MVT) with the new term called "task". Nowadays, this term is changed into "thread".[1] In 1997, "Simultaneous Multithread" (SMT) is defined by a group of scientist.
These techniques prove that it performs better than others.[2] In 2002, Intel applied a new multithreading technique into their Xeon server processor named Hyper-Threading Technology ¡is Intel's proprietary simultaneous multithread. Until now, this technology is still used in Intel's Core, for example, Intel's Skylake, Kaby Lake, Coffee Lake or Comet Lake — the newest Intel's Code name for its Core processor (Launched: August 21st, 2019) Processor I3]. AMD has also built their own commercial SMT processor, such as AMD Bulldozer microarchitecture FlexFPU (Launched: Late 2011)44 or AMD Zem microarchitecture (Launched: February 2017) [5]. — RISC-V research pieces: + RISC-V suitable for many modern techniques to handle the hazard, for example branch prediction, out-of-order or renaming in Dual pipeline superscalar RISC-V iii processor [6], RVCoreP — Soft Processor I7I BOOM Core[s}, FPGA-Optimized Out-of- Order RISC-V Soft Processor{9].
These processor all are applied most advantages techniques to enhance performance. + In cases of Multi-threaded RISC-V compliant processing core family for loT end nodes [10] and Efficient Mathematical Accelerator Design Coupled with an interleaved multi-threading RISC-V Microprocessor [11] , these processors are built based on Klessydra which is an open core with multithreaded architecture. Reasons chooses this project: — Multithreading is a technique that enhances the performance of single-core processor significantly, so it is used in a huge amount of commercial processors nowadays. Besides, RISC-V ISA is new, free and also support for synchronization.
That’s why, this project makes Vietnam keep up with the newest processor’s technology in the world. — Most of papers about multithread worldwide is designed based on an open core, such as Klessydra, which is too complicated and hard to modify. That’s why, in this project we consider to design an own multithreading processor with some techniques enhance performance. Project Objective: — Design a 32-bit pipelined RISC-V processor with the multithreading architecture suitable for executing RV32I and synchronization mechanism.
— Verify the processor by simulation on software and testing on an FPGA board. — Expected Frequency: 80Mhz. Methodology: — Theoretical research: iv + Understand the RISC-V instruction set architecture, especially RV32I and RV32A. + Understand some critical mechanisms, such as pipelined techniques and multithreading architecture.
— Design & synthesis: + Design and synthesis the netlist based on the Altera FPGA environment. — Simulation: + Draw on RTG to generate Assembly-code randomly for running simulation. — Practical: + Install the design and test on the Altera FPGA board. Main content and limitations: * Content 1: — Study about the RISC-V instruction set architecture: + Figure out the execution of instructions in RV32I.
+ Figure out the execution of 2 instructions for synchronizing — load reservation (Ir) and store condition (sc). + Figure out the 32-bit RISC-V instruction format. + Figure out the standard addressing mode of the RISC-V processor. — Method: + Reference some paper/book about RISC-V ISA, especially RV32I and RV32A.
+ Content 2: — Study pipelined techniques and multithreading architecture at the hardware level: + Figure out some practical ways to tackle hazards in multicycle processors. © Out-of-order. + Figure out some standard multithreading techniques for hardware: ¢ Coarse-grained multithreading. e Interleaved multithreading e Simultaneous multithreading — Method: + Reference some papers/books about handling hazards.
+ Reference some papers/books about multithreading processor. + Content 3: — Design datapaths for a pipelined RISC-V processor with multithreading architecture: + Design: PC, Architecture Register File, Renaming Register File, Reservation Buffer, ALU, Forward unit, Load Store Queue, Branch Target Buffer,. + Design memory block, such as Instruction and Data memory. — Result: + Complete all of the datapaths suitable for a 2-slot-threads processor.
+ Content 4: — Design controller to control the datapaths in a pipelined RISC-V processor with multithreading architecture: + Design controllers for one purpose: Fetch controller (switching controller), Decode Controller, Dispatch controller, Synchronize controller,. — Result: Complete controllers control the datapath work functionally. + Content 5: — Generate random Assembly-code by RTG to: + Verify the execution of one thread in the ModelSim environment. + Test one thread on the FPGA board.
vi + Verify the synchronizing mechanism of the multithread processor in the ModelSim environment. + Test the synchronizing mechanism of the multithread processor on the FPGA board. Implementation plans: No. | Task Duration Study about the RISC-V ISA: RV32I, load 1 01/03/2021 — 8/03/2021 (1 week) reservation and store condition.
Figure out some practical ways to tackle hazards in multicycle processors. 8/03/2021 —15/03/2021 (1 week) — Out-of-order. Figure out some standard multithreading techniques for hardware: — Coarse-grained multithreading. - Simultaneous multithreading Vii Design Datapath.
26/03/2021 — 17/05/2021 (3 weeks) Install and test on FPGA. 07/06/2021 — 25/06/2021 (2 weeks) Confirmation of Supervisor HCM City, March 24, 2021 (Signature and full name) Student (Signature and full name) Ho Ngoc Diem Le Nguyen Hoang Thien viii Chapter |. Integer Register-Register QperafiOIIs. Integer Register-Immediate InstruCtiOIIS.
Control Transfer InstTUC(ÏONS. Load/Store Instructions. Load Reservation/Store Condition InstruCtiOns. Advantage and drawbaCK.
Design OV€TVICW.- càng HH TH TH HH re. Overview of Instruction Fetch stage. Overview of Instruction Decode stage. Overview of Issue sfag€.
ch nh HH HH Hà Hye. Overview of Execute stage. sàn HH gu ớ. Overview of Write-Back stage.
Overview of Memory Access SfA8. tt re 21 Chapter 2. 23 "cố ốc cố ố ốốố ố ố. tt ng HH HH 10 TH HH g0.
63 E5 cố ốc cố cố ốốe. Architecture Register File (ARF). Renaming Register File (RRF) .- --- 5+ St St SE 112141111111 11111111111 1 1111 re,79 3. Verify with small tests 4.
Verify a myriad of test CaSCS occ Sàn 25 4.cc tt tình H111re. Test-case G€TI€TAẨOT. Standard Synchronization Problem.- - + 5+ s++x+x+t+zvEexererrveeeerereree 36 K UANA o0 c va. Harward Utilization and Max Frequency Report from Quartus.
Conclusion and Future Work. HH0 Trà 48 Appendix A. Instruction Set Arclit€CtUTC. - - - +65 S* vs ‡v‡kekrervkererekeerkrkreree 49 ALL.
HH 1 2 H001 H0 HT g1 010gr 49 F2. 5 1 ST E1 HH HH TH HH Appendix B.---- - -- 52525 5S S*2*2E2veEtErkrkrkerrrrrkrrrrrrree 60 6 St vkrkekekekrkrrrrrree 61 B. Non-Pipelined/Pipelined Processors. In-Order/Out-of-Order Processors.
Scalar/Superscalar PTOC€SSOFS. Multicore PTOC€SSOTS. ¿S1 HH HH Hiên B. Multicore Processors vs Multithreaded Processors xii B.1 101101111 Ha rờ 165 xiii LIST OF FIGURES Figure 1.1: RV32I user-visible architectural state [9].2: The system design of Multithreaded ProcesSSOT.3: The pipeline architecture of the multithreaded proCe$SOT.1: The system design of the DFOC€SSOT.-- ¿(6 + SS*xEkkerrererrkevek 22 Figure 2.2: The conversion from Assembly to Binary Code.3: The flow chart of the AssemblGr.4: The pipeline structure of the DFOC€SSOT.5: System design of Instruction Fetch stage .-- - - +52 5s c+c+x+xz+ese 28 Figure 2.6: System design of Instruction Decode stage.7: System design of Issue stage .8: System design of Execute S(ag€.9: System design of Write-Back and Mem-Access sfage.1: The flow chart of Pre-encoding of the Assembler .2: The flow chart of Convert step of the Assembler .3: The design of PC with thread switching mechanism.4: 2-bit prediction algOrithim.-- - - + ¿+ St +‡Ek*k#keEE+EEEEkEkekErkkrkrkekrree 68 XIV Figure 3.5: Inside of BTB block .6: The inside of instruction ITI€ITIOFY.7: The inside of Architecture Register File .8: The inside of Renaming Register File.9: The inside of Reservation Buffer for Branch .10: The inside of Reservation Buffer for ALU instruction .11: The inside of load-store QUeUle .12: The inside Arithmetic and Logic Execution Unit .13: The inside Branches Execution Unit.14: The inside of Load Controller .15: The inside of Store COntrOÏer.
¿+ ¿ 2 + 5++++x£++xv£v£zxexexererke 01 Figure 4.-------:- - 5c 52522222 re ren 04 Figure 4.2: Verification plan for small fŒS(. -- ¿+ 55+ xxx ‡v£vxvxereveerrerrre 07 Figure 4.3: The test case used for checking Out-of-Order execution.4: Waveform for Out-of-Order execution — Pre-simulation.5: Waveform for Out-of-Order execution — Post-simulation — At 55MHz.6: The test case used for checking Dynamic Branch Prediction .7: Waveform for Branch Prediction — Pre-Simulation .8: Waveform for Branch Prediction — Post-Simulation — At 55MHz.9: The test case used for checking Synchronize — Thread l.10 : The test case used for checking Synchronize — Thread 2.11: Waveform for Ir.12: Waveform for Ir.w — Post-Simulation — At 55SMHz.13: First assembly code for thread | used for context swi(ching.14: Second assembly code for thread 1 used for context switching.15: Third assembly code for thread | used for context switching.16: Fourth assembly code for thread 1 used for context switching.17: Fifth assembly code for thread 1 used for context switching.18: First assembly code for thread 2 used for context switching.19: Second assembly code for thread 2 used for context switching.