VIETNAM NATIONAL UNIVERSITY - HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING NGUYEN PHAN HOANG PHUC CAPSTONE PROJECT RESEARCH DESIGN A MULTI-CORE PROCESSOR BASED ON RISC-V INSTRUCTION SET ARCHITECTURE NGHIÊN CỨU THIET KE VI XỬ LÝ ĐA NHÂN DUA TREN KIEN TRÚC TẬP LỆNH RISC-V HO CHI MINH CITY, 2021 VIETNAM NATIONAL UNIVERSITY - HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING NGUYEN PHAN HOANG PHUC- 17520909 CAPSTONE PROJECT RESEARCH DESIGN A MULTI-CORE PROCESSOR BASED ON RISC-V INSTRUCTION SET ARCHITECTURE NGHIEN CUU THIET KE VI XU LY DA NHAN DUA TREN KIEN TRUC TAP LENH RISC-V BACHELOR OF ENGINEERING IN COMPUTER ENGINEERING SUPERVISOR M. HO NGOC DIEM HO CHI MINH CITY, 2021 LIST OF DEFENSE COMMITTEE Defense committee of the capstone project, established under Decision No. 462/QD- DHCNTT dated July 23, 2021 of Rector of the University of Information Technology. E — Commissioner ACKNOWLEDGMENT The basis of this research initially stemmed from my passion for developing a better architecture for a modern processor.
As the world moves further into the digital age, there will be more significant and more robust hardware, especially processors, to calculate and handle increasingly complicated programs. The low-performance processor will be outdated technology and removed to make room for the new one. How will we improve processor performance? It is my passion to find out and develop a new method to break down the limitation of processors today. In truth, I could not have achieved my current level of success without a strong support group.
First of all, all lecturers and staff at the University of Information Technology — VietNam National University - Ho Chi Minh City, who always teach a solid foundation of knowledge, especially the ones in the department of computer engineering, each of whom has given me opportunities to absorb expertise experience effectively. Secondly, I also appreciate my parents, who supported me with love and understanding. Finally, I am so grateful to Hồ Ngọc Diễm, who has provided patient advice and brightly guidance throughout the research process. Once again, thank you all for your unwavering support.
VIETNAM NATIONAL UNIVERSITY HCMC THE SOCIALIST REPUBLIC OF UNIVERSITY OF INFORMATION VIETNAM TECHNOLOGY Independence - Freedom - Happiness OUTLINE DETAILS VIETNAMESE NAME: NGHIEN CUU THIET KE BO VI XU LY DA LOI DUA TREN KIEN TRUC TAP LENH RISC-V ENGLISH NAME: RESEARCH DESIGN A MULTI-CORE PROCESSOR BASED ON RISC-V INSTRUCTION SET ARCHITECTURE Supervisor: M. Hé Ngoc Diém Start day — End day: From March 08, 2021 to June 25, 2021 Student: Nguyén Phan Hoang Phtic - 17520909 Content 1. Overview Whena single-core processor rapidly reaches complexity and speed limit. A multi-core processor is the simplest way to enhance processor performance.
This methodology is also a trend of developing processors in recent years to exploit entirely current bleeding-edge semiconductor technology. Besides, the RISC-V instruction set architecture (ISA) is being provided without charging any license fee, and it makes room for designing your own processor more effortlessly. The RISC-V community are well-known, and their processors have applied in numerous different SoC as well as boards; some of them are available for the commercial market. Researching relating work is a trend over the world: e Single-core RISC-V processor examples include RVCoreP and Skati processor.
These processors are multi-cycle processors that can perform base instructions, multiplication/division and floating-point operations (Especially Shakti processor is capable of executing atomic instructions). By implementing the Atomic standard extension, Skakti’s frequency decreased dramatically compared to RVCoreP, purely focusing on ALU optimization. Multi-core processors can be mentioned that is the quad-core processor designed by Manoj Kumar Gouda and D. ISA of this processor is not mentioned, and its memory is organized as centralized shared- memory.
Another multi-core processor is the many-core processor designed by Ahmed Kamaleldin team, which includes 36 cores and distributed shared-memory implementation. This processor can perform RV32I and two other extensions (RV32M and RV32C). Atomic operations are not applied to both processors. There are some free available cores similar to this work containing Pulpino RISCY, PicoRV32, Freedom.
Three processors are famous in the RISC-V community and often used as the core processor in other work. They can execute basic arithmetic & logic operations as well as compressed instructions. The drawbacks of these processors are that they include much auxiliaries hardware on the processor. These components may no need in other application and lead to performance reduction.
In Viet Nam, there is research relating to RISC-V ISA: The most recent research is designing a RISC-V processor with supervisor mode, which can execute the RV32I base instruction set and other system instructions. This work is in charge by An Xuan Tuan from the Faculty of Computer Engineering. Although this processor can handle exceptions and support supervisor mode, it only is implemented as a single-core processor. That is the reason why the operating frequency is limited to 12.
The first reason for researching is applying atomic instructions, a straight forward method to maintain synchronization in a multi-core processor but was not applied in the multi-core processor above to measure processor performance in each technique. Besides, no research is recorded in Viet Nam about designing a multi-core processor based on RISC-V ISA; this work will contribute to helping Viet Nam caught up with the world advancement in the integrated circuit design field in general and RISC-V processor in specific. Project objective Design a 32-bit multi-cycle processor that is capable of executing basic operations in the RV32I instruction set and their atomic extension RV32A. Design an arbitrator handles access memory violations that may occur during an execution time.
Verify the design by industrial methods. The operating frequency for the processor at least is 100 Mhz 3. Methodology Theoretical research method: Study about RISC-V instruction set architecture, multi-core micro-architecture, synchronization problem and coherence in a multi- core processor. Design & synthesis method: Design and synthesis the netlist based on Altera FPGA Design Flow.
Simulation method: Run simulation on ModelSim with test cases generated randomly by the RTG unit (Random test generator). Practical method: Embed and verify on the FPGA board (Using DE2 kit). Main content Design processor core includes PC, Register files, ALU, Hazard detection unit, Branching unit, Forwarding units,. Design data memory and instruction memory Design arbitrator unit Design simulation on Model Sim Test on the FPGA board 5.
Implementation plan Work description Time Research RISC-V architecture March 08, 2021 — March 14, 2021 (1 week) Research multi-core micro-architecture March 15, 2021 — March 21, 2021 (1 week) Design data memory and instruction memory March 22, 2021 — April 04, 2021 (2 weeks) Design processor core April 05, 2021 — May 02, 2021 (4 weeks) Simulate on Model Sim May 03, 2021 — May 16, 2021 (2 weeks) Test on the FPGA board May 17, 2021 — June 06, 2021 (3 weeks) Write the report June 07, 2021 — June 25, 2021 (3 weeks) Confirmation of supervisor HCM City, March 03, 2021 (Signature and full name) Student (Signature and full name) Hồ Ngọc Diễm Nguyễn Phan Hoàng Phúc TABLES OF CONTENTS Chapter 1. Introduction to instruction set architecture. RISC-V architecture OV€TVI€W. Comparison of instruction set architectures.
Details in RISC-V instruction set architeCfUTe. Introduction to microarChit€CUTC. Multi-core processor OV€TVIW. Memory coherence & consistency problem.
CPU system designn. th ng HT HH HT ngư 2 2. Data initialiZat[OI. Creating label hash tabÌe.
Reformat & splitting instructiOn. Verify and convert inSITUCtÏOI. Export the result to output ẨiÏ€s. Instruction memory design.
Data memory đ€SigI. cece ee SE SE k1 2212181 1111211 re. PTOC€SSOT COFC. S1 ST HH HH HH hà 50 Chapter 4.
Directed test verification. Test case Ø€T€TA(ÏONI. 6 + 1 vn HH HH HH gi T7 4. Test case manipulation.
Automation verification method.--- - - 2 + 5++++++++ce£zx+xexerereree 82 4. Random test V€TiÍÏCAfiOH. Riscv-tests V€TIÍICAfÏO. SG ST nh TH nh TH nh nh nàn như 85 4.- + SE 1k kg it 85 4.
POS(-SynLH€SIS. càng HH HH HT HH HH 87 4.--- -- 5:55 St St*E2EEE#ESEEEkekeEEkrrrkrkrkrrerkrrree 89 4.---- + 3S th tt TH H112 00. Conclusion & Future Work .- th HT HT HH HT HH HH 94 Appendix A. Introduction other instruction set architeCfUre.
X86 architecture OV€TVI€W. nh HH re96 A. ARM architecture OV€TVIW. MIPS architecture OV€TVICW.
Introduction other microarchit©CfUT€. Very long instruction Word processor. Out-of-order Processor. LIST OF FIGURES Figure 1.1: RV32I instructions formats .2: Example of CPU system design.------ - 5252555 5+scc>xzeseersrx 20 Figure 2.1: The general system đesign.----- + ¿5522 ++2St2txtxekerrererrrree 21 Figure 2.2: General algorithm of asseImbÏeT.3: General block diagTaIm.-- - ¿+ + + St S**E£k£k#EvErkekekekrrkrkrkererre 26 Figure 3.1: Flow chart for creating label hash table.2: Flow chart of SpÏitting.- 5c 55c sssseeeeeererrrerrrerece OO Figure 3.3: Flow chart of convert and verify instructiOn.4: The design of instruction I€IOYY.
¿+ s5 5+s+xs+s+vevxsxseeseeerxee DD Figure 3.5: Data memory schematic .--¿- ¿c6 St*‡EvekekerrrrkkrrekrkrrkrkreÐ Z Figure 3.6: Data memory parftÏOI.7: Schematic of sub_ data_ meim.8: Schematic of ari(€T. St t St SEEvEEEkskekekrkrrrrereerkrkrkrkrerrrd Al Figure 3.9: sub_arbitrator schematic .10: The pipeline S(TUCfUTC.11: the IF stage schematc.12: Schematic of the ID Stag€.--- - + c5 xv#EkErkekekekekrkrkrrrree 53 Figure 3.13: Schematic of the contTOÏer.-- + ¿<< +S+5++++x+xe+ez+xexexvxss+ 57 Figure 3.14:Schematic of the B stage .15: Schematic of the EX s(age€.---- - ¿552 2 Sr2t+t2tterrrrkrrerrrree 67 Figure 3.16: Schematic of the MEM stage. --- St steeerrrrrerrrree 71 Figure 3.17: Schematic of the WB stage.2: Test case generation flow. - -- c6 tt ngư 78 Figure 4.3: Data generator algorithm.4: File generator algOrithim.5: Automation verification process.6: Automation verification process (Cont.7: The LUI instruction eXeCUfiOH.--- - + ¿5-5 SE St+t+kevekerrkrkererre §6 Figure 4.8: The BNE instruction eX€CUtiOI.
6-5 tt svEvvexeeeserrrerree 86 Figure 4.9: The LR/SC sequence eX€CutiON.10: A parf of post-synthesize simulation waveform.11: Contents of data MeMory.12: Schematic of top level for FPGA implementation .- 90 LIST OF TABLES Table 1.1: Status of ISA base and ex†€nSIOIS. ¿cà tre 5 Table 1.2: Pros and cons of each ISA [3] .3: RISC-V register CONVENTIONS 0.4: RISC-V assembly language [2] .5: Advantages and drawbacks of mentioned microarchitectures.6: Relaxed consistency models .1: Bus system of the design .1: I/O interface of instruction memory design.2: I/O interface of data memory design .3: I/O interface of sub_data_memory design.4: I/O interface of sub_arbitrator .5: Writable boundaries corresponding to each COFe.6: I/O interface of arbitrator_ontrOlÏe-.-- + s2 s++ss+es+zs++sx+zs£zssz 47 Table 3.7: Memory operation TuÌ€S.8: Instruction decoding table .eccecceeecce cscs eeteneseseseeeesenesestsneseneseeeanes 49 Table 3.9: I/O interface of the IF stage.10: I/O interface ofthe ID stage .12: I/O interface of the controller oo. ccc cece 5< + +++£+s++££vzxzxeeexer+ 58 Table 3.13: control_field signal encoding.14: Instructions are decoded by ØTOUD.15: I/O interface of the B sfage.16: I/O interface of the EX stage .---- - ¿5:56 1+ ESx k2 2 2212111111111 te 68 Table 3.18: alu_control_ out signal đefinitiOn.--¿-- - 555+s<cc+xecveeerereesed 69 Table 3.19: I/O interface of the MEM sfage.20: I/O interface of the WB stage.1: Verification plan oo. ccc cseeseseeeenseeeessescsenseseesseseseseneeeessseessenseeneeeeee 75 Table 4.2: RV32A violation simulation reSuÏt.---------sc555++cvc++evrxereerrxey 84 Table 4.3: RTG Verificaiton result.
-- +6 5+5 SE2EE1Ek ST ng HH85 Table 4.5: Synthesis parameter cOnfiguratiOI.6: Fmax of the processor.-- 5° 552222 +$2StS*2E‡E£ESEvEkekekererkrkrkerrree 89 Table 4.8: The comparison to pipeline DTOC€SSOTS.9: The comparison to other multi-core DFOC€SSOTS.10: The comparison to popular RISC-V coTes.11: Pros and cons of the dual-core DTOC€SSOT.- - - ¿55555225 5+5+ 93 List of Acronym ISA Instruction set architecture RISC Reduced instruction set computer RV32I Risc-v 32 Interger RV32A Risc-v 32 Atomic SMP Symmetric multiprocessor DSM Distributed shared memory RMWs Read-Modify-Write instructions AMOs Atomic instructions FPGA Field Programmable gate array PC Program Counter UART Universal asynchronous receiver- transmitter RTG Random test generator Abstract The world always seeks a new architecture processor to speed up current computer performance. Many technology companies have invested their money to find new methods to accelerate their processors and achieve that purpose. Multi-core processor development is the most excellent technique and essential for any modern system because it is a practical and straightforward approach to enhance processor performance while developing a new hardware architecture is increasingly challenging and costly.