MINISTRY OF EDUCATION AND TRAINING HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION FACULTY FOR HIGH QUALITY TRAINING GRADUATION PROJECT ELECTRONICS AND COMMUNICATIONS DESIGN AND OPTIMIZATION OF APPROXIMATE ADDER USING ADVANCED CMOS TECHNOLOGY LECTURER: PhD. PHAM VAN KHOA STUDENT: LUONG NGOC PHUONG QUYNH NGUYEN PHUC HUNG SKL012497 Ho Chi Minh City, January 2024 HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION FACULTY FOR HIGH QUALITY TRAINING GRADUATION REPORT DESIGN AND OPTIMIZATION OF APPROXIMATE ADDER USING ADVANCED CMOS TECHNOLOGY Student: LUONG NGOC PHUONG QUYNH ID: 19161050 Student: NGUYEN PHUC HUNG ID: 19161013 Electronics and Communications Engineering Major: Technology Advisor: PhD. PHAM VAN KHOA Ho Chi Minh City, January 2024 I THE SOCIALIST REPUBLIC OF VIETNAM Independence – Freedom– Happiness -------- Ho Chi Minh City, January , 2024 GRADUATION PROJECT ASSIGNMENT Student name: Luong Ngoc Phuong Quynh Student ID: 19161050 _________________________ Student name: Nguyen Phuc Hung Student ID: 19161013 __________________________ Major: Electronics and Communications Class: 1916CLA Engineering Technology Advisor: Ph.D Pham Van Khoa Phone number: 0964720967 Date of assignment: 01/09/2023 Date of submission: 12/01/2024 1. Project title: Design and optimization of approximate adder using advanced CMOS technology 2.
Initial materials provided by the advisor: Materials about approximate computing, analysis method full adders design 3. Content of the project: Discovery to high-performance adders and optimize it into approximate adders, simulating based on 90nm cmos technology 4. Final product: Design diagrams and simulation data for XOR/XNOR circuits, Full Adder circuits, Approximate Adder CHAIR OF THE PROGRAM ADVISOR (Sign with full name) (Sign with full name) III THE SOCIALIST REPUBLIC OF VIETNAM Independence – Freedom– Happiness -------- Ho Chi Minh City, January , 2024 ADVISOR’S EVALUATION SHEET Student name: LuongNgoc Phuong Quynh Student ID: 19161050 Student name: Nguyen Phuc Hung Student ID: 19161013 Major: Electronics and Communications Engineering Technology Project title: Design and optimization of approximate adder using advanced CMOS technology Advisor: Ph.D Pham Van Khoa EVALUATION 1. Content of the project: Discovery to high-performance adders and optimize it into approximate adders, simulating based on 90nm cmos technology 2.
Strengths: Learned and resreached about the most optimal full adders and designed approximate adders such as Low-part Or Adder and Hardware Efficient Approximate Adder. Weaknesses: The performance of the 2 approximate adder (LOA and HEAA) has not been compared; resreach on other approximate adder has not been complated yet 4. Approval for oral defense? (Approved or denied) .(in words:…………………………………………………………) Ho Chi Minh City, January , 2024 ADVISOR (Sign with full name) IV THE SOCIALIST REPUBLIC OF VIETNAM Independence – Freedom– Happiness -------- Ho Chi Minh City, January , 2024 PRE-DEFENSE EVALUATION SHEET Student name: LuongNgoc Phuong Quynh Student ID: 19161050 Student name: Nguyen Phuc Hung Student ID: 19161013 Major: Electronics and Communications Engineering Technology Project title: Design and optimization of approximate adder using advanced CMOS technology Name of Reviewer: Ph.D Pham Van Khoa EVALUATION 1. Content and workload of the project Discovery to high-performance adders and optimize it into approximate adders, simulating based on 90nm cmos technology 2.
Strengths: Learned and resreached about the most optimal full adders and designed approximate adders such as Low-part Or Adder and Hardware Efficient Approximate Adder 3. Weaknesses: The performance of the 2 approximate adder (LOA and HEAA) has not been compared; resreach on other approximate adder has not been complated yet 4. Approval for oral defense? (Approved or denied) .) Ho Chi Minh City, January , 2024 REVIEWER (Sign with full name) V THE SOCIALIST REPUBLIC OF VIETNAM Independence – Freedom– Happiness -------- Ho Chi Minh City, January , 2024 EVALUATION SHEET OF DEFENSE COMMITTEE MEMBER Student name: LuongNgoc Phuong Quynh Student ID: 19161050 Student name: Nguyen Phuc Hung Student ID: 19161013 Major: Electronics and Communications Engineering Technology Project title: Design and optimization of approximate adder using advanced CMOS technology Name of Defense Committee Member: Ph.D Pham Van Khoa EVALUATION 1. Content and workload of the project Discovery to high-performance adders and optimize it into approximate adders, simulating based on 90nm cmos technology 2.
Strengths: Learned and resreached about the most optimal full adders and designed approximate adders such as Low-part Or Adder and Hardware Efficient Approximate Adder 3. Weaknesses: The performance of the 2 approximate adder (LOA and HEAA) has not been compared; resreach on other approximate adder has not been complated yet 4.) Ho Chi Minh City, January , 2024 COMMITTEE MEMBER (Sign with full name) VI THANK YOU During my time studying at Ho Chi Minh City University of Technical Education, I would like to express my sincere thanks to the School Board of Directors and the teachers for creating the best learning conditions and environment for me so that I can concentrate on studying and researching. Furthermore, I want to convey my sincere thanks to the professors and instructors at the Faculty of High-Quality Education for their commitment to teaching and for inspiring me to study more about every topic so that I may arm myself with the finest tools possible for the future. I want to express my gratitude to Ph.
Pham Van Khoa, my instructor, in particular, for his passionate guidance and advice. Throughout the composition of this research paper, he supported me, offered advice, and assisted with editing so that I could finish my graduation thesis as effectively as feasible. However, my research cannot be perfect owing to restricted conditions and expertise. I so eagerly await your input so that I may improve my writing and add to my expertise for next research projects.
These are insightful remarks that will aid me in the future in refining both my thesis and my expertise. Finally, I would want to thank you very much again and wish you continued health, happiness, and professional success. VII SUMMARY In order to handle an ever-increasing amount of data, computer systems' overall energy consumption is still rising alarmingly quickly, despite advancements in semiconductor technology and the development of energy-efficient design strategies. In particular, computer systems are being utilized more and more to handle vast amounts of data from diverse sources and interact with the real environment as they become more and more commonplace.
In addition, we anticipate that they will exhibit realistic human interfaces and context awareness. As a result, a vast array of applications—known as Recognition, Mining, and Synthesis, or RMS—have surfaced, and they now consume a substantial amount of computational resources in a variety of computing contexts, from large-scale data centers to mobile and Internet of Things (IoT) devices. In order to handle the increasing amount of data, it is imperative to significantly increase the energy efficiency for these new workloads. Thankfully, these applications typically include an inherent error-resilience characteristic.
They handle redundant and noisy data from unconventional input sources, such different kinds of sensors (inexact inputs), and the corresponding methods are frequently stochastic (e. Furthermore, these applications typically do not need to calculate a singular or ideal numerical result (i., "acceptable" outputs rather than exact ones). Ensuring error-free calculations becomes more and more energy-intensive as semiconductor technology moves closer to the nanoscale range. This is because at advanced technology nodes with low supply voltage and constantly rising integration density, circuits are more susceptible to errors and fluctuations in parameters.
For variation tolerance and error correction, guardbands and redundancies are needed at different levels of the design hierarchy in conventional fault-free computing, which results in a large energy overhead. Inspired by the aforementioned difficulties, approximation computing has emerged as a highly promising alternative that has gained considerable support in both academia and industry. Aiming for large energy-efficiency advantages, approximation computing intentionally inserts "acceptable errors" into the computing process by loosening the numerical equivalency between the design and implementation of error-tolerant applications. VIII TABLE OF CONTENTS GRADUATION PROJECT ASSIGNMENT .III ADVISOR’S EVALUATION SHEET.
IV PRE-DEFENSE EVALUATION SHEET .V EVALUATION SHEET OF DEFENSE COMMITTEE MEMBER. VI THANK YOU. VIII TABLE OF CONTENTS. IX TABLE OF FIGURE .XI TABLE OF TABLE .XIV Chapter 1 : INTRODUCTION.
2 Chapter 2 : THEORETICAL BASIS .1 The Full Adder Circuit .1 The CLRCL (Complementary & Level Restoring Carry Logic) Full Adder 7 2.2 High-gate-count full adder designs (TG-CMOS, TFA, 14T, 16T) .3 The 10T Full Adder Design .2 The XOR/XNOR circuits .1 The 8T XOR-XNOR .2 The 10T XOR-XNOR circuit .3 The 4-transistor XOR/XNOR circuits .3 Approximate XOR/XNOR-based Adders design .2 Approximate Circuits And Their Implementation .4 Process Design Kit .1 Generic Process Design Kit (GPDK) 90 nm technology (gpdk90) .2 Generic Process Design Kit (GPDK) 180 nm technology (gpdk180). 31 Chapter 3 : CONSTRUCT THE IDEAL APPROXIMATE ADDER .1 Optimal Design Quality .1 Optimization of XNOR .2 Optimization of full adder: .2 Optimization of Adder design methods .1 Optimization of Adder design methods: Low-part OR Adder (LOA) .2 Optimization of Adder design methods: Hardware Efficient Approximate Adder (HEAA). 51 Chapter 4 : RESULTS OF SIMULATION, COMPARISON, ANALYSIS AND SYNTHESIS .1 Results of simulation by Cadence .1 A comparison delay of each full adder in 90, 180nm: 10T adder (90nm and 180nm) .2 A comparison power of each full adder in 90, 180nm 10T adder (90nm and 180nm) .2 Analysis of result .1 A software tool for automatic generation of approximate arithmetic circuits56 4.3 Relation of the computing approximate_LOA (Lower-Part Or Adder Design), 10T, XOR/XNOR .2 Relation of the computing approximate_HEAA (Hardware Efficient Approximate Adder Design), 10T, XOR/XNOR. 63 Chapter 5 : CONCLUSION AND DEVELOPMENT DIRECTION .67 X TABLE OF FIGURE Figure 2- 1 The symbol of full adder .5 Figure 2- 2 Block Diagram of basic full adder circuit.
7 Figure 2- 3 Logic circuit diagram of a 2-bit full adder. 7 Figure 2- 4 Logic block diagram of the CLRCL full adder. 8 Figure 2- 5 MOS circuit schematic design of the CLRCL full adder. 9 Figure 2- 6 The Full Adder circuit using transmission gates.
10 Figure 2- 7 The TFA (Transmission Function Adder) full adder. 12 Figure 2- 8 The 14T full adder design. 12 Figure 2- 9 The 16T full adder design. 13 Figure 2- 10 The 10T full adder design.
14 Figure 2- 11 The 8-transistor XOR/XNOR circuits. 15 Figure 2- 12 10-transistor XOR/XNOR circuits. 16 Figure 2- 13 The 4-transistor XOR/XNOR circuits. 18 Figure 2- 14 Accurate XOR/XNOR-based 10T Full-Adders .19 Figure 2- 15 Conventional 10T full adder designs: The New Static Energy-Recovery Full (SERF) Adder.
20 Figure 2- 16 Architecture of lower-part OR adder (LOA) .21 Figure 2- 17 Operation of proposed adder .23 Figure 2- 18 Operations of proposed error reduction when An−k−1 and Bn−k−1 are identical. 24 Figure 2- 19 Operations of proposed error reduction when An−k−1 and Bn−k−1 are exclusive .24 Figure 2- 20 Approximate Adder (HEAA) Design. 25 Figure 2- 21 Approximate XOR-based Adder 1 (AXA1).25 Figure 2- 22 Approximate XNOR-based Adder 2 (AXA2).26 Figure 2- 23 Approximate XNOR-based Adder 3 (AXA3).28 Figure 2- 24 Process Design Kit (PDK) provides necessary information for the circuit design. 30 Figure 3- 1 Schematic of 4T XOR-XNOR circuit.
32 XI Figure 3- 2 Waveforms of the outputs of 4T XOR/XNOR circuit. 33 Figure 3- 3 TPHL and TPLH of 4T XNOR circuit. 33 Figure 3- 4 The average power of 4T XNOR.34 Figure 3- 5 Schematic of 8T XNOR .34 Figure 3- 6 Waveforms of the outputs of 8T XOR/XNOR circuit. 35 Figure 3- 7 TPHL and TPLH of 8T XNOR .35 Figure 3- 8 The average power of 8T XNOR.36 Figure 3- 9 Schematic of 10T XOR/XNOR circuit .36 Figure 3- 10 Waveforms of the outputs of 10T XOR/XNOR circuit.
37 Figure 3- 11 TPHL and TPLH of 10T XNOR .37 Figure 3- 12 The average power of 10T XNOR.38 Figure 3- 13 Schematic of SERF Full Adder. 39 Figure 3- 14 Waveforms of the outputs of SERF Full Adder circuit.39 Figure 3- 15 TPHL and TPLH of SERF Full Adder. 40 Figure 3- 16 The average power of SERF. 40 Figure 3- 17 Schematic of TFA Full Adder .