VIETNAM NATIONAL UNIVERSITY HANOI UNIVERSITY OF ENGINEERING AND TECHNOLOGY THI-THUY NGUYEN COMMUNICATION CONTROL MECHANISM IN RECONFIGURABLE NETWORK-ON-CHIPS ARCHITECTURES MASTER’S THESIS OF ELECTRONICS – TELECOMMUNICATIONS TECHNOLOGY Hanoi - 2015 TIEU LUAN MOI download : skknchat@gmail.com VIETNAM NATIONAL UNIVERSITY HANOI UNIVERSITY OF ENGINEERING AND TECHNOLOGY THI-THUY NGUYEN COMMUNICATION CONTROL MECHANISM IN RECONFIGURABLE NETWORK-ON-CHIPS ARCHITECTURES Branch: Electronics – Telecommunications Technology Major: Electronics Engineering Code: 60520203 MASTER’S THESIS OF ELECTRONICS – TELECOMMUNICATIONS TECHNOLOGY Supervisor: Assoc. Xuan-Tu Tran Hanoi - 2015 TIEU LUAN MOI download : skknchat@gmail.com 1 AUTHORSHIP “I hereby declare that the work contained in this thesis is of my own and has not been previously submitted for a degree or diploma at this or any other higher education institution. To the best of my knowledge and belief, the thesis contains no materials previously published or written by another person except where due reference or acknowledgement is made.” Signature:……………………………………………… TIEU LUAN MOI download : skknchat@gmail.com 2 TABLE OF CONTENTS AUTHORSHIP. 1 TABLE OF CONTENTS.
2 List of Figures. 5 List of Tables. 8 List of Abbreviations. 12 NETWORK-ON-CHIP.
Basic components of a NoC. Quality of the service. Communication mechanism in NoC. Definition and classification.
30 PROPOSED COMMUNICATION CONTROL MECHANISM IN RECONFIGURABLE NOCS ARCHITECTURES. Target reconfigurable NoC architectures. 30 TIEU LUAN MOI download : skknchat@gmail. Proposed Communication control mechanism.
Tracking and replacing routing information mechanism. 41 ARCHITECTURE OF MODIFIED ROUTER AND NETWORK INTERFACE. Modified architecture for reconfigurable network router. 54 VERIFICATION, IMPLEMENTATION AND EVALUATION.
Verifying basic function of NI. Verifying the mechanism of tracking and replacing routing information. 68 TIEU LUAN MOI download : skknchat@gmail. 70 TIEU LUAN MOI download : skknchat@gmail.com 5 List of Figures Figure 1-1: An example architecture of a 2D mesh.
13 Figure 1-2: Popular NoC topologies: (a) ring and chordal ring; (b) fat-tree; butterfly fat-tree; (d) 2D-mesh; (e) 2D-torus; (f) 2D folded torus [5]. 14 Figure 1-3: Three frequent routing modes of NoC: (a) Store And Forward; (b) Virtual Cut Though; (c) Wormhole [5]. 16 Figure 1-4: Four popular buffering strategies of NoC: (a) Input queuing;(b) Output queuing;(c) Virtual output queuing;(d)Virtual channel priority input queuing [5]. 18 Figure 1-5: Deadlock example [5].
20 Figure 1-6: Separated buffer virtual channels are used to solve the deadlock problem. The data of one VC can use the physical link when the others one in the same port is stalled[4]. 20 Figure 1-7: An example of livelock. The ouside routers can’t reach the inside once because they are in deadlock [5].
21 Figure 1-8: The classification of NOC’s flow cotrol mechanisms. 22 Figure 1-9: Connection implementation of end-to-end flow control [13]. 24 Figure 1-10: NoC architecture with injection level flow control strategy [14]. 25 Figure 1-11: Router architecture [15].
26 Figure 1-12: Proposed idea of T-error [12]. 27 Figure 1-13: Logic level of T-error [12]. 27 Figure 2-1: RNOC router architecture [2]. 32 Figure 2-3: The prohibited router appears just before or just after the corner of the routing path [2].
33 Figure 2-4: Block diagram of proposed communicaiton mechanism. 34 Figure 2-5: Router-to-router/NI interface and send/accept protocol [23]. 35 Figure 2-6: A flow diagram of the tracking and replacing routing information mechansim. 37 Figure 2-7: Structure of header flit.
38 TIEU LUAN MOI download : skknchat@gmail.com 6 Figure 2-8: Structue of body flit of a normal packet. 39 Figure 2-9: A structue of body flit of a special packet. 39 Figure 2-10: A structue of tail flit. 39 Figure 3-1: Micro-architecture of INPUT PORT of RNOC’s router [2].
42 Figure 3-2: Modifying the VC_Demux of the North input port. 43 Figure 3-3: Modifying the VC_Demux of the East input port. 44 Figure 3-4: Modifying the VC_Demux of the South input port. 44 Figure 3-5: Modifying the VC_Demux of the West input port.
44 Figure 3-6 : A architecture of NI. 45 Figure 3-7: C2R_buffer module. 46 Figure 3-8: C2R_controller module. 47 Figure 3-9: Flitizer module.
48 Figure 3-10: Routing table module. 49 Figure 3-11: Updating path module. 50 Figure 3-12: R2C_Buffer module. 51 Figure 3-13: R2C_controller module.
52 Figure 3-14: De_flitizer module. 53 Figure 4-1 Testbench model. 55 Figure 4-2: Test case 1. 56 Figure 4-3: Simulation for tracking phase and processing phase in test case 1.
57 Figure 4-4: Simulation for replacing phase in test case 1. 57 Figure 4-5: Test case 2. 58 Figure 4-6 Simulation for tracking phase and processing phase in test case 2. 59 Figure 4-7: Simulation for replacing phase in test case 2.
59 Figure 4-8: Test case 3. 60 Figure 4-9: Simulation for tracking phase and processing phase in test case 3. 61 TIEU LUAN MOI download : skknchat@gmail.com 7 Figure 4-10: Simulation for replacing phase in test case 3. 61 Figure 4-11: Timing information.
62 Figure 4-12: ASIC & VLSI design flow [24]. 70 TIEU LUAN MOI download : skknchat@gmail.com 8 List of Tables Table 2-1: Function and code for each type of flits. 38 Table 3-1: Codes for directions. 43 Table 3-2: Code for VC_Demux of each input port.
43 Table 3-3: Pin desciption of C2R_buffer module. 46 Table 3-4: Pin desciption of R2c_buffer module. 51 Table 4-1: Routing informaton in test case 1. 57 Table 4-2: Routing information in test case 2.
58 Table 4-3: Rouiting information in test case 3. 60 Table 4-4: Device Utilization Sumary (estimated values). 61 Table 4-5: Delay information. 63 TIEU LUAN MOI download : skknchat@gmail.com 9 List of Abbreviations ASIC Application-Specific Integrated Circuit CCM Communication Control Mechanism FIFO First In First Out FPGA Field Programmable Gate Array IP Intellectual Property NoC Network on Chip QoS Quality of Service SAF Store -And-Forward SoC System on Chip VC Virtual Channel VCPIQ Virtual Channel Priority Queuing VCT Virtual Cut Through VHDL VHSIC Hardware Description Language VHSIC Very High Speed Integrated Circuit VOQ Virtual Output Queuing WH Wormhole TIEU LUAN MOI download : skknchat@gmail.com 10 INTRODUCTION To meet the quickly increasing in demand of applications, more and more computing resources such as Central Processing Units, Digital Signal Processors, and particular Intellectual Property (IP) cores are added into a System-on-Chip (SoC).
Therefore, interconnection between these computing resources become a big challenge in SoC. Network-on-Chip (NoC) have recently emerged as a promising solution for communication in large SoCs. The NoC architecture provides a new method for connecting of different IP-cores through an effective, modular, and scalable network [1]. However, standard NoCs architectures seem not flexible enough to support dynamic environment where communication characteristics can strongly changing at run-time.
A new NoC design methodology called reconfigurable NoCs emerges an alternative solution to tackle current challenges. Reconfigurable NoCs have the ability to provide adaptive communication infrastructures and the flexible network protocols [1].Thanks to dynamically reconfiguring hardware ability, reconfigurable NoCs allow many hardware tasks to be mapped onto the same hardware platform. There are several proposed reconfigurable NoCs, and each architecture has a different method to make NoC reconfigurable. Depending on the characteristic and features of each reconfigurable NoC, communication infrastructures and communication protocol change adaptively after the reconfiguring process.
As be a part of the communication protocol, the communication control mechanisms (CCM) also need to be updated with a new environment to ensure the correct operation as well as the communication performance of the network. The RNoC [2] is a reconfigurable NoC platform developed at the key laboratory for Smart Integrated Systems (SIS lab), VNU University of Engineering and Technology. It provides a router architecture which can reconfigure the routing path when the being transmitted data face to prohibited node (i. However, the routing path reconfiguration process leads to an increase in packet delay.
In the other words, the process of reconfiguration lengthens the period the packet occupy communication resources and thus affect to network traffic. Therefore, we will propose a CCM for the RNoC platform to guarantee the lossless communication as well as reduce the packet delay of the network. TIEU LUAN MOI download : skknchat@gmail.com 11 In our CCM, both the node-to-node flow control and the end-to-end flow control are used to reach the target. While the node-to-node flow control ensures the lossless communication of RNoC, the end-to-end flow control is responsible for updating the CCM after reconfiguration process.
The main part of our end-to-end flow control is the tracking and replacing information mechanism. To implement our tracking and replacing information mechanism, the RNoC architecture will be modified to support the tracking phase while NI architecture is designed to implement the processing phase, replacing phase. Our NI design is modeled by using VHDL language. Then our NIs are plugged into a 4×4 mesh modified RNoC platform for simulating and verifying the operation of our CCM.
The simulation results show that our CCM helps NoC decrease about 23.5% to 50% in header-to-header delay, 0% to 50% in tail-to-tail delay and 5.7% in packet-to-packet delay. After the verification process, our NI architecture is synthesized to kit Virtex5 XC5VLX330 -2ff1760 using tools of Xilinx. The result of synthesis process gives that our design can operate at a maximum frequency of 294MHz. The thesis is organized into four chapters, the Introduction section and Conclusion section.
Chapter 1 will give an overview of the NoC and its basic concepts. Besides, the communication mechanism in NoC and reconfigurable NoCs are also reviewed in this chapter. Chapter 2 is about our proposed communication control mechanism for reconfigurable NoC architectures. Then, the modified architecture of RNoC router and our NI design are described in Chapter 3.
In Chapter 4, the method to simulate and verify our design will be explained. The implementation results and the evaluation are also given in chapter 4. Finally, conclusions section will summarize the work presented and give the future work which far related. TIEU LUAN MOI download : skknchat@gmail.com 12 NETWORK-ON-CHIP In this chapter, we will address on basic concepts of network-on-chip (NoC) paradigm.
Then the communication control mechanism will also be presented. Finally, some previous works will be reviewed and discussed to provide the state of the art of the research topic. Basic concepts Network on chip (NoC) is emerging as a revolutionary methodology in solving the bandwidth bottleneck of shared bus interconnection.In this section, to give a good overview of NoC, we will introduce main concepts of NoC paradigm. The network topology, communication mechanisms, routing modes, buffering strategies, routing algorithms, quality of service, flow control and data blocking are explained and analyzed.
After that, the state of the art about NoC will give the investigating trend which the topic of this thesis is clearer. Basic components of a NoC There are three fundamental components in a Network-on-chip: Routers, Network Interface (NI) or Network Adapter (NA) and links [3]. In NoC, routers connect to each other through links with a specific topology. An example architecture of a 2D mesh NoC example is shown in Figure 1-1.
Each router can communicate with an IP- core through a NI. TIEU LUAN MOI download : skknchat@gmail.com 13 Figure 1-1: An example architecture of a 2D mesh. Links: A communication link is a set of wires. The function of links is physically connecting routers in the network and actually implementing the communication [3].
Router: the main function of a router is routing data from source to destination according to chosen protocol and routing strategy [4]. Architecture of router depend on many factors such as communication protocol, routing mode, routing algorithm, … Network Interface (or Network Adapter): As each IP-core may have a distinct interface protocol with respect to the network, NoCs must include NIs which makes the logic connection between IP-cores and the routers [3]. Network topology Network topology of NoC defines how the network routers are interconnected by channels and is usually modeled by a graph [5]. There are many topologies can be used to implement NoC, and each of them owns advantages and drawbacks.