VIETNAME NATIONAL UNIVERSITY HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FALCURY OF COMPUTER ENGINEERING DAO VINH HIEN- 17520489 NGUYEN VU QUANG VINH- 17521265 GRADUATE THESIS Ap dung cac ky thuat cia DFT (Design For Testability) vao Arm Cortex M0 Applying DFT (Design For Testability) Techniques To Arm Cortex M0. ASIC Design Engineering HO CHI MINH CITY, 2021 VIETNAME NATIONAL UNIVERSITY HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FALCURY OF COMPUTER ENGINEERING DAO VINH HIEN- 17520489 NGUYEN VU QUANG VINH- 17521265 GRADUATE THESIS Ap dụng các kỹ thuật của DFT (Design For Testability) vào Arm Cortex M0 Applying DFT (Design For Testability) Techniques To Arm Cortex M0. ASIC Design Engineering INSTRUCTOR Phd. NGUYEN MINH SON Master.
NGUYEN DUY MANH THI HO CHI MINH CITY, 2021 THONG TIN HOI DONG CHAM KHÓA LUẬN TOT NGHIỆP Hội đồng cham khoá luận tốt nghiệp, thành lập theo Quyết định số 462/QD-DHCNTT ngày 23 tháng 07 năm 2021 của Hiệu trưởng Trường Đại học Công Nghệ Thông Tin PREFACE First of all, we would like to express our sincere thanks to all the teachers and students of the University of Information Technology — Vietnam National University Ho Chi Minh city, especially the teachers of Computer Engineering, who have facilitated us to learn a lot of knowledge and experience throughout the learning period. In particular, we would like to sincerely thank Dr. Nguyen Minh Son and Mr. Nguyen Duy Manh Thi who have guided our group very enthusiastically throughout the course of the project, supporting and providing us with valuable knowledge so that our group can complete the topic well.
Moreover, we would also like to thank our friends, colleagues who have helped us to improve our project, to exchange and solve our problem conscientiously during implement the thesis. Finally, we would like to thank our parents for always creating favorable conditions and spiritual support throughout the course of the dissertation. Despite great efforts, our knowledge and experience are still limited, so the report cannot avoid many shortcomings. We are looking forward to receiving many comments from teachers.
Once again, we would like to sincerely thank you! Ho Chi Minh City, 30 June 2021 Students Dao Vinh Hien Nguyen Vu Quang Vinh §):2890/0//. INTRODUCTION ABOUT DFT & CONCEPTS. Design for Testability. Typical Scan Insertion flow [6].
Create Test PTOtOCOl. _ Insert Scam Pathe. DFT DRC Coverage. ccc ec ecseseseseeeeseseseeesseseseseessesescsesseseneaeaees 8 1.
Concepts in DFT method. What is Scan Techniqu€?. Scan Insertion Technique. Modeling silicom errr.
Fault Coverage, Test COV€TABe. ch HH HH. Sàn HH HH He. _ Scan Signals and Some Problems Applying Scan Insertion.
Automatic Test Pattern Generation A'TPG. SCAN COMPRESSION TECHNIQUE. ARM CORTEX-M0 & SYSTEM DESIGN OVERVIEW. Full Cortex-MŨ prOC€SSOT.
DesignStart’s Cortex-M0 processor. DesignStarfs example design. STRUCTURE BLOCK AFTER SYNTHESIS. BUILD ENVIRONMENT & ANALYZE ECO DFET.
THE TECHNIQUE WE USED. compile_delete_unloaded_sequential_cells. compile_seqmap_identify_ shit_ regiS€TS. compile seqmap Identify_ shift_registers_with_synchronous_ logic 4 3.
test_disable_enhanced_ dft_ drc_ reporting. auto_wire_load_ seleCfiOI. verilogout_show_unconnected_Dpin .---- 5+5 c+s+ceceeexev 48 compile_seqmap_propagate_constant .---- - - + 55555 c248 compile_seqmap_enable_output_inversion. case_analysis_with_logic_constants.
xxx vn HH ng iưy 50 3. test_scan_in_port_naming style wo. tes(_scan_out_por(_naming_ S(yÏ@. Se(_sCan_COnÍT#UTA{ÏOH.
TepOor(_ dt_ COnfigurafiONI. T€POF_ SCan_ COnẨiØUTAfÏOH. eee eee EEEEEkeEEEEEEkrkekrrrrkee 60 3. THHH HH TH HH HH 62 3.
set_ dft_insertion_ COnfÏØuTatiOH. set_fix_multÏpÏ€_ DOF(_ I€fS. report(_scan_pat(Hh.---6-+- ch tt HH1. EU TT 8s iZ:iddđdđdidddididỶẮỶẮỶẮỶẰAAAAAẮIẮIẮIẮẰẮAẰAA.
write test model. COMMECE_MEt eo. SETTING FOR SCAN COMPRESSION |. Set_scan_compression_confiøuratiOH.
Why do we need to fix DRC violatiOn?. DRC Rule DI, D2, D3, D9, D7. (5S tt HH HH0. c1 1S HH HH HH.
Report DFT_DRC violation. càng HH Hit 91 A1. Test COV€TAB€. TH HH it94 4.
Scan COImpT€SSiOH. Report DFT_DRC violatiOn. Test COV€Tage. Limitations of the topic.
Development direction of the topic. 15 FIGURE LIST Figure 1.1 Design using Boundary Scan Design [7].2 Design using Memory BISTT.3 The operation of MBIST .4 Design using BIST Logic .5 Scan Insertion Process [6] .6 Design before and after applying Scan.7 Non-scan Flip Flop [7] .8 Multiplexer Flip Flop [7] .9 Multiplexer Latch Master-Slave [7] .----¿-++-+-+-ec+xexseexee+ 2 Figure 1.10 Operation of two clock signals [7] .--- - es ¿+55 <+c+cecczxzxseerer+ 3 Figure 1.11 Scan Cell type Clocked Scan for Flip Flop [7].12 Scan Cell Type Clocked Scan for Latches [7].13 Single Latch and Single Latch LSSD [7] .14 LSSD Single Latch Structure [7].------- --+-+5++<+s+sece>xz++eeesr+ 6 Figure 1.15 A pair of latches and Double Latch LSSD [7] .16 Double Latch LSSD [7] .17 Flip Flop and Clocked LSSD Type Cell Scan for Flip Flop [7].18 Clocked LSSD Type Cell Scam [7].-- --¿-+:+<+<<sc+xz++ceeer+ 20 Figure 1.19 Flip Flop and Auxiliary Clocked LSSD Cell Scan.20 Scan Cell type Auxiliary Clocks LSSÌD.24 Partition Scan in Desigin.--- + 5S St xui 25 Figure 1.25 Scan chain in a block (Partition A).26 Clock through Clock Gating .27 Clock signal via Clock Gating processed.28 Clock signals go through many logics.29 Clock signals go through multiple processed Logics.30 Clock signals used as data .31 Uncontrollable reset signal.32 Uncontrollable Clr signal.------ - + ¿+ £+£+£++k+xe£e£erzxzxererre 30 Figure 1.33 Asym syncable reset signal processing compiler cannot be controlled 31 Figure 1.34 Asym syncable clear signal processing compiler cannot be controlled 31 Figure 1.35 The ATPG technique model .----¿- ¿+ ¿5+5 ++*‡*+£‡£sx+kekzererersee 33 Figure 1.36 Differences between two scan MOdE .37 Example for Test Cycle Savings [7].38 Codec StTUC{UTC.39 Decompressor Logic Structure Example for 4-to-8 Decompressor .40 Compressor Logic Structure Example for 8-to-4 Compressor.1 Functional block diagram of Cortex-M0.2 Simplified block diagram of Cortex-MO Processor 39 Figure 2.3 Functional block diagram of DesignStart’s Cortex-M0 Processor.4 Simplified block diagram of DesignStart’s Cortex-MO Processor.5 Example microcontroller system top level view .6 Block diagram of DesignStart’s example system.7 Design after Synthesis step .1 Setup environment variable .2 Set up library to USG.3 Set timing for testing and define necessary signal to reduce DFT DRC 'ViOÏALÏON.4 Scan in & Scan out port naming S(yÏG-. ¿+ + +sx+x+xzvzervxeee 53 Figure 3.5 Setup Scan ConfiguiratiOH.6 The result of report_ dft_configuration.7 The result of report_scan_ confÏðuratiOI. «+ + sece+xeecerveee+l 60 Figure 3.8 Example of setup to check DFT DRC violation of pre and post.9 Schematic before insert_dft oo.
cece eee eeseeeseseeseseseetsesteseeeeeeeeees 64 Figure 3.10 Schematic after inserf_ dÍ(.---- - - ¿55+ kex*EvEzk+kekekrrkrkrkereree 64 Figure 3.11 Write out report to check & write output for next s(ep .12 Example of ECO fix Reset DRC violations .13 Setting for scan COIDT€SSỈOH.-- - ¿52 5S 2+ St+t+EEekerrkrkererrk 76 Figure 3.14 DFT DRC Violation .- óc <5 tt SE vskekekEkrrrrrererekekrkrkrerrre 78 Figure 3.15 Input CLK of FF was not controlled .16 Input SET of FF was not controlled .17 Input RST of FF was not controlled.18 Input CLK of FF not active when clocks are set on.19 Input CLK of FF couldn't capture dafa.20 State loop at output ŸY,.21 Insert Mux cell into design to fix violation.22 Insert Mux before input CLK .23 Insert Mux before input SETB .24 Insert Mux before input RSTB .25 Insert Mux before input CLK.26 Insert Mux before input CLK.27 Insert Mux before input A2 .28 Insert Mux before common point of inputs CLK .29 Insert Mux before common point of inputs SET/RST.30 Insert Mux before common point of inputs CLK .31 Example of scripts fix DI violations .32 Example of scripts fix D2/D3 violations.----- 5-5-5 c+cs<++ 90 Figure 09)009)00 na.2 Scan chains & number of flipflops per chain .3 Scan chain with each Scan in & Scan out coressponding with.4 Test coverage before run DFT ECO.5 Test coverage after run DFT ECO.6 FF 0 before insert IDT.- - ¿+ + SE +k‡k‡kEkEEEEkEkEEEEEkrkekererkek 95 Figure 4.7 FFs 1, 2, 3 before insert IDET.8 FFs 4, 5, 6 before insert IDFT. 6 xxx srrerrrerereksrkrkrerrri 97 Figure 4.9 Scan chain 6 FFs after insert DT. --¿5+55+s+s+sec++x+xsxvsex+ 98 Figure 4.11 Scan chain 1 in SCheimat(C. - ‹- - 6 5+ sxS++Eevsketevrerererereervreree 00 Figure 4.12 First 10 scan FFs in chain Ì.13 dft_dre violation after using scan compr€§SION.14 Scan chains & number of flipflops per chaïn .15 Each scan chain in compression mode .16 Test coverage when using Scan COMPFESSION .17 Added ports after scan €OIpF€SSIOH.18 Scan chain 21 in scan COmpressiON .19 First 6 scan FFs in chain 21 .21 Scan_Ins & Decompressor .22 Decompressor decompress data to scan chains .24 Compressor & SCAN_ OUTTs.25 Compressor compress data from scan chain to Scan_OUTs.- - + - St St TT HH0 0g rớy 13 TABLE LIST Table 1.1 Two modes of operation of Multiplexer Latch Master-Slave.2 Clocked Scan's two operating modes for latches.3 Master Latch's truth tabÌe.- -¿- + - + 5+ SE re 17 Table 1.4 Slave Latch's fact table.5 Truth table of LSSD Type Cell Scan.-- ¿+ 55c 5+ c+ccx+ssrsrersee 20 Table 1.6 Auxiliary Clocked LSSD truth table.1 Items in DesignStart’s example SySf€mm.
- 6 + St kg 110 LIST OF ABBREVIATION ABBREVIATION FULL MEANING DFT Design for Testability IC Intergrated Circuit SoC System on Chip BIST Built-in Self Test RTL Register Transfer Level TC Test Coverage ECO Engineering Change Order FC Fault Coverage LSSD Level Sensitive Scan Design ATPG Automatic Test Pattern Generation DRC Design Rule Checks ATE Automatic Test Equipment TATR Test Application Time Reduction TDVR Test Data Volume Reduction THESIS SUMMARY In recent decades, the microelectronics industry has made rapid progress thanks to its high-density, integrated lead technology. The development of micro-electronic technology is favorable conditions for other industries to develop such as Information Technology, Telecommunications Electronics,. and especially in every consumer electronic product has the contribution of microelectronic technology. With many applications as above, the research of integrated microchip technology - Application-Specific Integrated Circuits (ASICs) is very necessary for the current period especially in our country, so I have implemented the topic "Design for Test design for signal processing chip".
The topic covers the basics of the application- oriented integrated circuit design process (System on Chip flow). The topic delves into the research and application of DFT (Design for Test) techniques to ensure the ability to test silicon errors, also known as manufacturer-made errors for chips after they have been produced. Through the process of implementing the topic, we have understood the basic knowledge of micro-circuit design technology as well as related micro-electronic knowledge. The topic is done with a serious working attitude and best efforts, but this is a new field, knowledge is limited so it is impossible to avoid errors.
We look forward to receiving the comments of teachers and friends to improve the topic. INTRODUCTION ABOUT DFT & CONCEPTS 1. Design for Testability 1. General As we all know, as the size and complexity of integrated circuits (IC) increase, error checking becomes more difficult.
Design for Testability (DFT) is basically meant for providing a method for testing each and every node in the design for structural and other faults. Higher the number of nodes which can be tested through the targeted number of patterns, greater is the test coverage of the design. For this to be possible, every node in the design has to be controllable and observable. DFT technique allows designers to create products with the highest error checking and most time-saving capabilities.
The ability to check for errors is a property of a design, it determines the possibility of being able to create a program to test all possible errors of the designed design produced. Previously, the design and error checking were two separate processes, the inspection was carried out only after completing the design cycle. But in today's design cycle, inspections will be combined into the design process that forms an implementation process called DFT in design. It should be noted that the DFT technique only detect the manufacturing's FAULT (open, short.
in die), not detect design FAULT (wrong function). However, the highest error checking capacity never reaches 100% because there will always be positions in the design that we will not be able to test. DFT Techniques This section will cover some DFT techniques. Boundary Scan Design [6][7] Boundary scan is a DFT technique that simplifies printed circuit board testing using a standard chip-board test interface.