VIETNAM NATIONAL UNIVERSITY HO CHI MINH CITY HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY TRUONG MINH SON INTEGRATING DMAIC FRAMEWORK AND DBSCAN CLUSTERING ALGORITHM FOR ENHANCED QUALITY ASSURANCE IN SEMICONDUCTOR MANUFACTURING Major: Industrial Engineering Major code: 8520117 MASTER’S THESIS THIS THESIS IS COMPLETED AT HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY – VNU-HCM Supervisor: Assoc. Do Ngoc Hien Examiner 1: Dr. Le Duc Dao Examiner 2: Dr. Nguyen Van Thanh This master’s thesis is defended at HCM City University of Technology, VNU- HCM City on June 8th, 2024.
Master’s Thesis Committee: (Please write down full name and academic rank of each member of the Master’s Thesis Committee) 1. Nguyen Vang Phuc Nguyen 2. Nguyen Duc Duy 3. Le Duc Dao 4.
Nguyen Van Thanh 5. Do Ngoc Hien Approval of the Chair of Master’s Thesis Committee and Dean of Faculty of Mechanical Engineering after the thesis being corrected (If any). CHAIR OF THESIS COMMITTEE DEAN OF FACULTY OF MECHANICALENGINEERING i VIETNAM NATIONAL UNIVERSITY - HO CHI MINH CITY SOCIALIST REPUBLIC OF VIETNAM HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY Independence – Freedom - Happiness THE TASK SHEET OF MASTER’S THESIS Full name: Truong Minh Son Student ID: 2270222 Date of birth: 08/04/1995 Place of birth: Vung Tau City Major: Industrial Engineering Major ID: 8520117 I. THESIS TITLE (In Vietnames): KẾT HỢP PHƯƠNG PHÁP DMAIC VÀ THUẬT TOÁN DBSCAN TRONG VIỆC CẢI TIẾN VÀ ĐẢM BẢO CHẤT LƯỢNG TRONG NGÀNH CÔNG NGHIỆP BÁN DẪN II.
THESIS TITLE (In English): INTEGRATING DMAIC FRAMEWORK AND DBSCAN CLUSTERING ALGORITHM FOR ENHANCED QUALITY ASSURANCE IN SEMICONDUCTOR MANUFACTURING. TASKS AND CONTENTS: − Identifying the current problem at root cause at Flipchip attach operation in a semiconductor manufacturing company. − Solving the problem by establishing an approach solution to machine learning which alternate traditional Quality control method. − Evaluate the effectiveness of model through practical implementation and next research orientation.
THESIS START DAY: 15/01/2024 V. THESIS COMPLETION DAY: 20/05/2024 VI. Đỗ Ngọc Hiền Ho Chi Minh City, June 8th, 2024 SUPERVISOR HEAD OF DEPARTMENT (Full name and signature) (Full name and signature) DEAN OF FACULTY OF MECHANICAL ENGINEERING (Full name and signature) ii ACKNOWLEDGEMENT First and foremost, I extend my gratitude to the professors at the University of Technology, Ho Chi Minh City, who imparted valuable knowledge to me. Their teachings have been instrumental in my personal growth and have enriched my understanding of life.
Their support has facilitated my learning and the completion of this research project. I would also like to express my appreciation to the leadership and various departments at Intel Products Vietnam Co. For their warm reception and the favorable conditions they provided for me to access and understand technological processes. Special thanks go to Associate Professor Dr.
Do Ngoc Hien, my thesis advisor. His dedicated guidance throughout the project has been invaluable. Not only did he provide essential knowledge, but he also offered practical examples that deepened my understanding of the subject matter. His enthusiastic instructions allowed me to apply theoretical concepts effectively in real-world scenarios.
In this report, I draw upon the knowledge he imparted, along with my own insights gained during the learning process, to address the challenges encountered. During my internship, I faced numerous difficulties, transitioning from uncertainty to gaining experience. The unwavering support of my professors and the enthusiasm of colleagues at the company helped me acquire precious insights, enabling me to successfully complete this course and write this graduation report. My heartfelt thanks to all involved.
Ho Chi Minh city, 8st June 2024 Author Truong Minh Son iii ABSTRACT In today’s rapidly advancing semiconductor technology landscape, the competitive market has become increasingly fierce. Optimizing processes within assembly and testing companies, especially those dealing with semiconductor units, plays a crucial role in boosting profitability and enhancing competitive capabilities. A research is about semiconductor chip assembly and testing, operates critical production lines with multiple essential stages. Among these stages, the Flipchip attach process has been identified as a significant contributor to contamination issues affecting product quality.
In this report, the author provides an overview of the production process at Assembly, focusing on the Flipchip attach operation. They identify persistent challenges and prioritize addressing pressing concerns. The report also introduces theoretical foundations, including the DMAIC (Define, Measure, Analyze, Improve, Control) methodology, to pinpoint issues, analyze root causes, and propose effective solutions. To improve defect detection during the die attachment process to substrates, the report proposes an enhancement using the DBSCAN (Density-Based Spatial Clustering of Applications with Noise) algorithm.
The results demonstrate that DBSCAN efficiently identifies dust particles, enabling timely intervention in subsequent production stages and ensuring the highest product quality. TÓM TẮT Trong bối cảnh công nghệ bán dẫn ngày càng phát triển nhanh chóng, thị trường cạnh tranh đã trở nên khốc liệt hơn. Tối ưu hóa quy trình trong các công ty lắp ráp và kiểm tra, đặc biệt là những công ty đang xử lý các đơn vị bán dẫn, đóng một vai trò quan trọng trong việc tăng cường lợi nhuận và nâng cao khả năng cạnh tranh. Bài nghiên cứu về một công ty chuyên về lắp ráp và kiểm tra chip bán dẫn, vận hành các dây chuyền sản xuất quan trọng với nhiều giai đoạn cần thiết.
Trong số các giai đoạn này, quá trình gắn chip đã được xác định là một nguyên nhân đóng góp quan trọng đối với vấn đề ô nhiễm ảnh hưởng đến chất lượng sản phẩm. Trong bài báo này, tác giả cung cấp một cái nhìn tổng quan về quy trình sản xuất tại bộ phận lắp ráp, tập trung vào hoạt động gắn chip. Họ xác định các thách thức dai dẳng và ưu tiên giải quyết các vấn đề cấp bách. Bài nghiên cứu cũng giới thiệu các nền tảng lý thuyết, bao gồm phương pháp DMAIC (Define, Measure, Analyze, Improve, Control), để xác định vấn đề, phân tích nguyên nhân gốc và đề xuất các giải pháp hiệu quả.
Để cải thiện việc phát hiện khuyết tật trong quá trình gắn die vào substrate, bài báo đề xuất sử dụng thuật toán DBSCAN (Density-Based Spatial Clustering of Applications with Noise). Kết quả cho thấy rằng DBSCAN hiệu quả trong việc xác định các hạt bụi, giúp can thiệp kịp thời trong các giai đoạn sản xuất tiếp theo và đảm bảo chất lượng sản phẩm cao nhất. iv THE COMMITMENT OF THE THESIS’AUTHOR I hereby declare that this thesis was carried out by myself under the guidance and supervision of Assoc. Do Ngoc Hien; and that the work contained and the results in it are true by author and have not violated research ethics.
The data and figures presented in this thesis are for analysis, comments, and evaluations from various resources by my own work and have been duly acknowledged in the reference part. In addition, other comments, reviews and data used by other authors, and organizations have been acknowledged, and explicitly cited. I will take full responsibility for any fraud detected in my thesis. Ho Chi Minh city, 8st June 2024 Author Truong Minh Son v CONTENTS THE TASK SHEET OF MASTER’S THESIS.
iv THE COMMITMENT OF THE THESIS’AUTHOR. v LIST OF FIGURE. ix LIST OF TABLE .2 Problem and solution introduction .4 Scope and constraints. 3 LITTERATURE REVIEW AND METHODOLOGYS .1 Six Sigma and DMAIC Framework .2 DBSCAN Clustering Algorithm .3 Integrating DMAIC and DBSCAN for Quality Assurance .2 Overview about Flipchip Attach operation .1 Flip Chip Attach process .2 Overview about Bonding machine .3 FlipChip Attach key process parameters .4 Flip Chip Attach key failure mode .3 Current state and Define problem .3 Measure the problem .4 Analyze the problem .4 Script Qualification process .2 Control phase after implementation.
44 CONCLUSION AND RECOMMENDATION .2 Evaluation of study .1 Advantages of study .2 Disadvantages of study .4 Recommendation for future research. 51 APPENDICE B – Python code. 64 vii LIST OF FIGURE Figure 2.3 Cause and Effect diagram (Fishbone diagram) .6 FMEA example template .7 Methodology using DMAIC model .1 Image a CPU Chip product (a) and structure cross section (b). Assembly-Test-Finish Manufacturing Process .3 Flipchip Attach module tool configuration .4 Media Tray Bundle (a) and single media tray (b) .5 Bonding machine concept.
Bonding process using TCB technology (a) and complete unit after bonding (b).7 Lot level and Unit level data. Top failure mode excursion event in 2022-2023 .9 RPN for NCO/NonWet and SBB failure mode .10 SBB failure mode cross section. Pareto chart for main contributor of SBB .12 Material analysis for FM element evaluation. Fishbone diagram of FM sourcing .14 FM present in Bond stage.
FM present underneath of substrate. SPC unit level limit for ContactHeight and DeltaHeight with less flexibility. Many over reject (false alarm) if revise the current Unit level limit. Data flow process .4 More than 1 cluster during validation .5 Noise factor Outlier at pocket level .6 Data validation after Eng rule applied .7 FM observed on all cases triggered .8 SQL pathfinder query .9 Script host for DBSCAN script running .10 Automail notification for operator take prompted response.
FMEA template to document improvement .12 RPN Before and After do improvement .13 Occurrence of SBB before and after improvement .1 Logic process of the algorithm. 51 ix LIST OF TABLE Table 2.1 Tools used for Define phase .2 Tools used for Measure phase .3 Tools used for Analyze phase.4 Tools used for Improvement phase .5 Tools used for Control phase .6 Tools are using in each methodology step .2 Flipchip attach failure mode description .1 Matrix for Valid and Invalid issue .1 Methodology process result .1 Background Integrated circuits (ICs), commonly referred to as microchips or computer chips, play a pivotal role in modern electronic devices. These compact chips consist of interconnected components, including transistors, resistors, and capacitors, etched onto a single piece of semiconductor material, typically silicon. Their widespread use in computers, smartphones, and televisions enables essential functions such as data processing and storage.
ICs have revolutionized electronics by enabling device miniaturization and enhanced functionality. As technology rapidly evolves, ICs continue to improve in performance while shrinking in size, following the trajectory predicted by Moore’s Law [1]. This evolution brings forth new challenges for semiconductor manufacturing companies. The increasing complexity of manufacturing processes, one of the mentioned challenges, makes maintaining stringent quality control standards becoming more difficult.
This report focused on a case study of a critical assembly plant within a global semiconductor company. Responsible for several final stages of chip manufacturing, this plant faces immense pressure to maintain product quality. To prevent the “Garbage in, garbage out” phenomenon and enhance early failure detection, quality control efforts concentrated on the initial stage of the entire process: Flip Chip Attach module. In this module, chips are inverted to connect solder dots with underlying electronics or circuit boards.2 Problem and solution introduction Currently, the challenges within the Flip Chip Attach module stem from managing process parameters, which significantly impact chip quality.
Specifically, the adoption of advanced Thermal Compression Bonding (TCB) methods introduces issues such as thermal coefficient of expansion mismatches, temperature gradients, misalignment, tilt, and process-induced stress and warpage [2]. Additionally, foreign materials (FM), including dust, dirt, and unintentional contamination from the environment, affect product quality. All semiconductor products are sensitive to FM, making its control crucial, not only in this module, but throughout the entire manufacturing process. In 1993, Harold has stated the effect of microcontamination will impact directly to yield and reliability of the semiconductor device [3].
Hence, control 1 microcontamination and reduce defect losses induced by microcontamination are the challenge in semiconductor manufacturing processes. The proposed solution to the quality challenges faced in Flip Chip Attach module involves the integration of two robust methodologies: the DMAIC (Define, Measure, Analyze, Improve, Control) framework and the DBSCAN (Density-Based Spatial Clustering of Applications with Noise) algorithm.