VIETNAM NATIONAL UNIVERSITY HO CHI MINH CITY HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY NGUYỄN ĐỨC NAM POLAR CODE DECODER HARDWARE DESIGN FOR 5G IMPLEMENTED ON FPGA/ASIC Major: Electronics Engineering Major code: 8520203 MASTER’S THESIS HO CHI MINH CITY, January 2024 THIS THESIS IS COMPLETED AT HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY – VNU-HCM Supervisor: Doctor Trần Hoàng Linh Examiner 1: Doctor Bùi Trọng Tú Examiner 2: Doctor Nguyễn Minh Sơn This master’s thesis is defended at HCM City University of Technology, VNU- HCM City on January 12th 2024 Master’s Thesis Committee: 1. Associate Professors – Doctor Trương Quang Vinh : Chairman 2. Associate Professors – Doctor Hoàng Trang : Commissioner 3. Doctor – Nguyễn Lý Thiên Trường : Secretary 4.
Doctor – Bùi Trọng Tú : Reviewer 1 5. Doctor – Nguyễn Minh Sơn : Reviewer 2 Approval of the Chair of Master’s Thesis Committee and Dean of Faculty of Electrical and Electronics Engineering after the thesis being corrected (If any). CHAIR OF THESIS COMMITTEE DEAN OF FACULTY OF ELECTRICAL AND ELECTRONICS ENGINEERING ii VIETNAM NATIONAL UNIVERSITY - HO CHI MINH CITY SOCIALIST REPUBLIC OF VIETNAM HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY Independence – Freedom - Happiness THE TASK SHEET OF MASTER’S THESIS Full name: Nguyễn Đức Nam Student ID: 2070356 Date of birth: 29-04-1996 Place of birth: Bà Rịa – Vũng Tàu Major: Electronics Engineering Major ID: 8520203 I. THESIS TITLE (In Vietnamese): THIẾT KẾ PHẦN CỨNG GIẢI MÃ CỰC (POLAR CODE) CHO 5G THỰC HIỆN TRÊN FPGA/ASIC II.
THESIS TITLE (In English): POLAR CODE DECODER HARDWARE DESIGN FOR 5G IMPLEMENTED ON FPGA/ASIC III. TASKS AND CONTENTS: To design and implement a polar code SC decoder on an FPGA using Verilog, improve the throughputs of the Semi-parallel Successive Cancellation. To reduce latency cycles by improving the architecture to decode the codeword in parallel based on the Semi-parallel Successive Cancellation. To improve fmax by analyzing and reducing the most critical delay path of the Semi-parallel Successive Cancellation.
To evaluate the performance of the FPGA-based polar code implementation in terms of resource utilization, fmax, latency, throughput. THESIS START DAY: 4/9/2023 V. THESIS COMPLETION DAY: 18/12/2023 VI. SUPERVISOR: DOCTOR TRẦN HOÀNG LINH Ho Chi Minh City, date 18/12/2023 SUPERVISOR HEAD OF DEPARTMENT (Full name and signature) (Full name and signature) DEAN OF FACULTY OF ELECTRICAL AND ELECTRONICS ENGINEERING (Full name and signature) iii ACKNOWLEDGEMENTS During my time studying and training at Ho Chi Minh City University of Technology, I received enthusiastic guidance and teaching from teachers, especially teachers working at the Department of Electrical and Electronics Engineering have imparted to me theoretical and practical knowledge over the past time.
During the process of writing my thesis, I received encouragement, guidance and valuable help from teachers, family and friends. With the deepest respect and gratitude, I would like to send my sincere thanks to the teachers of Ho Chi Minh City University of Science and Technology, the teachers of the Department of Electrical and Electronics Engineering - those who are constantly enthusiastic and inspiring to gain valuable knowledge for us. In particular, I would like to send my sincere thanks to my instructor - Dr. Tran Hoang Linh.
Over the past time, thanks to your enthusiastic help and guidance, I have had valuable and useful experiences. Your comments, encouragement and encouragement are the driving force for me to try my best to complete this thesis. Through this, I also send my sincere thanks to my family, friends and especially my parents - who always care, support and assist me in successfully completing this thesis. With limited time and limited experience, the thesis will inevitably have shortcomings.
I look forward to receiving comments and guidance from teachers so that I can improve, supplement knowledge, raise awareness and better serve practical work in the future. I sincerely thank you. Best regards, Ho Chi Minh City, date 18/12/2023 Nguyễn Đức Nam iv ABSTRACT This thesis demonstrate an effective field-programmable gate array (FPGA) implementation of successive-cancellation (SC) decoder for Polar code that is standard in 5G wireless system. We focus on improving the best contribution architecture Semi- parallel SC decoder.
Based on that, we show that the SC decoder of length N can be further optimized by decoding the codeword in parallel to reduce N/2 latency cycles, and improve max clock frequency by refining architecture of the process elements. We demonstrate an FPGA implementation of the decoder architecture for a 1024-bit- length polar code and show that our FPGA decoder can achieve more 50% throughput comparing to the Semi-parallel SC decoder without significantly increasing the hardware resources. TÓM TẮT LUẬN VĂN THẠC SĨ Luận án này chứng minh việc triển khai mảng cổng lập trình trường (FPGA) một cách hiệu quả của bộ giải mã successive-cancellation (SC) cho mã Polar – mã tiêu chuẩn trong hệ thống không dây 5G. Chúng tôi tập trung vào việc cải thiện kiến trúc của thiết kế đóng góp tốt nhất Bộ giải mã SC bán song song (Semi-Parallel SC Decoder).
Dựa trên đó, chúng tôi cho thấy bộ giải mã SC có độ dài N có thể được tối ưu hóa hơn nữa bằng cách giải mã các từ mã một cách song song để giảm chu kỳ độ trễ N/2 và cải thiện tần số tối đa bằng cách tinh chỉnh kiến trúc của các bộ tính toán giải. Chúng tôi chứng minh việc triển khai FPGA của kiến trúc bộ giải mã cho mã cực có độ dài 1024 bit và cho thấy rằng bộ giải mã FPGA của chúng tôi có thể đạt được thông lượng cao hơn 50% so với bộ giải mã SC bán song song mà không làm tăng đáng kể tài nguyên phần cứng. v THE COMMITMENT The author hereby declares that this is his own research work. The research results and conclusions in this thesis are truthful, and are not copied from any source or in any form.
References to sources (if any) have been cited and reference sources recorded according to regulations. Thesis author, Nguyễn Đức Nam Ho Chi Minh University of Technology Ho Chi Minh City, date 18/12/2023 vi TABLE OF CONTENTS 1.2 Related science researching .3 Tasks and expected results .1 Polar Code Construction and Encoding .2 Successive Cancellation (SC) Decoding .3 Semi-parallel SC decoder. MAIN DESIGN, ALGORITHM OF THE THESIS .2 Optimized PE Implementation .4 Partial Sum Registers .5 Partial Sum Update Logic .6 Frozen Channel ROM .1 Polar Code Encoder & Decoder on Matlab .2 Polar Code Decoder Simulation on Model Sim .3 Polar Code Decoder Function test on FPGA DE10 .4 Polar Code Decoder Synthesis Result on FPGA Stratix IV. CONCLUSION AND FUTURE IMPROVING WORK .42 vii LIST OF FIGURES Figure 1-1 Roadmap of channel coding in wireless communication systems.2 Figure 2-1 Polar code encoder with N=8.6 Figure 2-2 Butterfly-based SC decoder with N=8 .8 Figure 2-3 Scheduling for the butterfly-based SC decoder with N=8 .9 Figure 2-4 Scheduling and LR data flow graph of a semi-parallel SC decoder with N=8 and P=2.
11 Figure 2-5 Utilization rate 𝛼𝑆𝑃 and relative-speed factor 𝜎𝑆𝑃 for the semiparallel SC decoder. 13 Figure 2-6 Semi-parallel SC decoder architecture. 14 Figure 2-7 Sign and magnitude processing element architecture. 17 Figure 3-1 Enhanced semi-parallel SC decoder high-level architecture.
18 Figure 3-2 Schedule for original reference and enhanced semi-parallel SC decoder. 19 Figure 3-3 RTL architecture of a standard PE. 21 Figure 3-4 Mirrored decoding graph for N=8. 22 Figure 3-5 Organization of the LLR memory for N=8 and P=2 with uniform memory block size.
24 Figure 3-6 Architecture of the partial sum registers with N=8. 25 Figure 3-7 Frozen Channel ROM. 28 Figure 3-8 RTL design of the stage number. 29 Figure 3-9 RTL design of the portion 𝑝𝑠 of a stage.
29 Figure 3-10 RTL design of the LLR memory read/write address. 30 Figure 3-11 RTL design of the partial sum register read address. 30 Figure 3-12 RTL design of the F/G function selecting signal. 30 Figure 4-1 Polar code system with BPSK-AWGN channels.
31 Figure 4-2 MATLAB test bench data generating scripts. 32 Figure 4-3 Test bench data generated by MATLAB. 32 Figure 4-4 BPSK modulation over an AWGN channel. 33 viii Figure 4-5 ModelSim test bench scripts.
35 Figure 4-6 Memory loading and decoding process in ModelSim. 35 Figure 4-7 Model Sim simulation result. 36 Figure 4-8 Function test on FPGA DE10. 37 Figure 4-9 Resource usage.
38 Figure 4-10 Max clock frequency result. 38 Figure 7-1 Flow Summary. 42 Figure 7-2 Flow Non-Default Global Settings. 42 Figure 7-3 Flow Elapsed Time.
43 Figure 7-4 Analysis & Synthesis Summary. 43 Figure 7-5 Analysis & Synthesis Settings. 44 Figure 7-6 Analysis & Synthesis Source Files Read. 44 Figure 7-7 Analysis & Synthesis Resource Usage Summary.
45 Figure 7-8 Analysis & Synthesis Resource Utilization by Entity. 45 Figure 7-9 Analysis & Synthesis Post-Synthesis Netlist Statistics for Top Partition. 46 Figure 7-10 Fitter Summary. 46 Figure 7-11 Fitter Settings.
47 Figure 7-12 Fitter Resource Usage Summary. 47 Figure 7-13 Fitter Resource Utilization by Entity. 48 Figure 7-14 Timing Analyzer Summary. 48 Figure 7-15 Timing Analyzer SDC File List.
49 Figure 7-16 Timing Analyzer Clocks. 49 Figure 7-17 Timing Analyzer Fmax Summary at Slow 900mV 85C Model. 50 Figure 7-18 Timing Analyzer Fmax Summary at Slow 900mV 0C Model. 50 Figure 7-19 Timing Analyzer Multicorner Timing Analysis Summary.
51 Figure 7-20 MATLAB decoder results, same as original message (1-12 test cases). 52 Figure 7-21 ModelSim decoder simulation and verification results (1-12 test cases). 53 ix Figure 7-22 MATLAB decoder results, same as original message (13-24 test cases). 54 Figure 7-23 ModelSim decoder simulation and verification results (13-24 test cases).
55 x LIST OF TABLES Table 1-1 Comparison implementation for 1024-bit polar codes using SCD architectures on Stratix IV FPGA.4 Table 4-1 Simulation result, frame error rate of polar codes of length N = 1024 the SC decoding of the 3GPP 5G standard under offset min-sum decoding. All simulations were performed using BPSK modulation over an AWGN channel. 34 Table 4-2 Comparison of our result for 1024-bit polar codes with other architectures on Stratix IV FPGA. 39 xi Master’s Thesis Supervisor: Doctor Trần Hoàng Linh 1.1 Overview In 2008, Arıkan [1] introduced polar codes as a significant theoretical breakthrough aimed at achieving the capacity of symmetric channels.
These codes are grounded in the concept of channel polarization, wherein the combination and division of channels lead to the transformation of a set of N identical binary-input discrete memoryless channels (B-DMC) into a group of polarized channels. Within this transformation, some channels become noiseless, approaching a capacity of one (termed as good channels), while others become noisy, with their capacity diminishing to zero (referred to as bad channels). This innovative approach enables the optimization of channel performance through strategic channel polarization techniques. As the channel number, or code length, approaches infinity, the proportion of good channels to the total channels converges toward the capacity of the original channel.
This phenomenon distinguishes polar codes from traditional channel codes like Turbo/LDPC codes. Polar codes introduce a novel concept in coding design, departing from the conventional approaches and showcasing a unique perspective on optimizing communication systems. In practical applications, channel coding serves as a crucial technology for ensuring reliable transmission, particularly in wireless communications. Figure 1-1 illustrates the progression of channel code applications across 3G to 5G wireless systems.
This roadmap highlights the pivotal role of channel coding in advancing the reliability and performance of wireless communication technologies over the years. The 5G systems introduce more stringent requirements for transmission latency (1ms) and reliability (99.999%), posing challenges that traditional Turbo codes struggle to meet.
