VIETNAM NATIONAL UNIVERSITY HO CHI MINH CITY HO CHI MINH UNIVERSITY OF TECHNOLOGY -------------------- TRAN DINH LONG MODELLING AND CONTROL OF ACTIVE NEUTRAL POINT CLAMPED MULTI-LEVEL INVERTER Major: Electrical Engineering Major ID: 8520201 MASTER THESIS HO CHI MINH CITY, February 2023 THIS RESEARCH IS COMPLETED AT: HO CHI MINH UNIVERSITY OF TECHNOLOGY – VNU HCM Instructor: Assoc. Nguyen Van Nho. Truong Phuoc Hoa. Tran Thanh Ngoc.
Master’s Thesis is defended at HCMC University of Technology, VNU- HCM on February 04, 2023 The Board of The Master’s Thesis Defense Council includes: 1. Nguyen Dinh Tuyen 2. Nguyen Chan Viet 3. Truong Phuoc Hoa 4.
Tran Thanh Ngoc 5. Council Member: Dr. Huynh Van Van Verification of the chairman of the Master’s Thesis Defense Council and the Dean of the Faculty of Electrical and Electronics Engineering after the defense is correct (if any). CHAIRMAN OF THE COUNCIL DEAN OF FACULTY OF (Full name and signature) ELECTRICAL AND ELECTRONICS ENGINEERING (Full name and signature) VIETNAM NATIONAL UNIVERSITY HCMC SOCIALIST REPUBLIC OF VIETNAM VNUHCM UNIVERSITY OF TECHNOLOGY Independent – Liberty - Happiness MASTER’S THESIS ASSIGNMENTS Full name: TRAN DINH LONG.
Date of birth: October 24th,1997 .Place of birth: HCMC. Major: Electrical Engineering. TITTLE: Modelling and Control of Active Neutral Point Clamped Multi-level Inverter Mô hình hoá và điều khiển bộ nghịch lưu tích cực. ASSIGNMENTS AND CONTENTS:.
Modelling the 5L ANPC with CBPWM method Modelling the 5L ANPC with SVPWM method Proposed SVPWM method to reduce Common-mode voltage. ASSIGNMENT DELIVERING DATE : September 5th,2022. ASSIGNMENT COMPLETING DATE: December 18th,2022. Nguyen Van Nho.
Ho Chi Minh City, December 16th, 2022 INSTRUCTOR HEAD OF DEPARTMENT (Full name and signature) (Full name and signature) DEAN OF FACULTY OF ELECTRICAL AND ELECTRONICS ENGINEERING (Full name and signature) i ACKNOWLEDGEMENTS Give the best sincerely to Associate Professor Nguyen Van Nho who has guided me through the thesis process. His expertise in this field of study is exceptional, and it was a pleasure and honour for me to have him as an advisor. I would like to thank Mr. Pham Dang Khoa and the members of PERLAB for assisting and encouraging me.
Finally, I sincerely thank my family for all the support they have given to me over the years Ho Chi Minh City, December 19th 2022 Student Tran Dinh Long ii ABSTRACT Multi-level inverters (MLIs) have been increasingly used practically. There are three main types: Neutral-Point-Clamped (NPC), Flying Capacitor (FC), and Cascade where NPCs are mostly used due to the simple structure and low cost. Three-level (3L) and five-level (5L) NPC have become the solution for higher power applications, which create better THD and CMV performance. The 5L NPC inverter has several problems such as different voltage ratings of diodes, and difficulty in balancing DC link voltage.
Active NPC (ANPC) has been introduced combining the robustness of the NPC and the d flexibility of the FC. There are many PWM methods to control the ANPC as CBPWM and SVPWM: CBPWM is simple and SVPWM is effective to reduce or eliminate the CMV. The proposed content of this thesis: SVPWM, CMV reduction and FC balancing. TÓM TẮT LUẬN VĂN Bộ nghịch lưu ngày càng được sử dụng phổ biến trong thực tế.
Có 3 dạng chính của nghịch lưu là NPC, FC và cascade, trong đó NPC được sử dụng nhiều do cấu trúc đơn giản và giá thành tiết kiệm. Với các thiếu bị đòi hỏi công suất và điện áp cao, NPC 3 bậc và 5 bậc được phát triển nhằm tăng THD và giảm CMV. Bộ nghịch lưu NPC 5 bậc xảy ra những khuyết điểm như khó cân bằng điện áp DC link, và điện áp giữa các diode khác nhau. Vì thế, nghịch lưu tích cực đã ra đời, là sự kết hợp giữa NPC và FC.
ANPC thường được điều khiển bằng phương pháp CBPWM là phương pháp đơn giản, trong đó SVPWM lại mang hiệu quả cao hơn trong việc giảm hoặc triệt tiêu CMV. Mục tiêu đề ra của luận văn nhằm đề xuất phương pháp SVPWM giảm dòng CMV và cân bằng điện áp FC. iii DECLARATION I certify that the work has not been submitted previously. The content of the thesis is the result of work which has been carried out since the official commencement date of the thesis Tran Dinh Long iv TABLE OF CONTENTS ACKNOWLEDGEMENTS.
ii TÓM TẮT LUẬN VĂN. iii LIST OF FIGURES .vi LIST OF TABLES. Overview of the 5L-ANPC .1 The 5L-ANPC Topology .2 Analysis of the 5L-ANPC .3 Principle of Capacitor Voltage Balancing. Carrier-based PWM for the 5L-ANPC inverter .1 Literature review for the CB-PWM.2 Flow chart of the CB-PWM algorithm.
Space Vector PWM for the 5L-ANPC.1 Proposed SVPWM for 5L-ANPC .2 Voltage balancing of the FC. Proposed SVPWM to reduce Common mode voltage .1 Common mode voltage (CMV) .2 Proposed SVPWM method to reduce CMV .1 Carrier-based PWM .1 Overview of losses calculation method. Conclusion and Future Works. 50 List of Publications.
65 vi LIST OF FIGURES Figure 1-1:NPC inverter topology and FC inverter topology. 2 Figure 2-1: Structure of 5L-ANPC inverter. 4 Figure 2-2: Switching state S1. 7 Figure 2-3: Switching state S2.
8 Figure 2-4: Switching state S3. 9 Figure 2-5 Switching state S4. 11 Figure 2-6: Switching state S5. 12 Figure 2-7: Switching state S6.
13 Figure 2-8 Switching state S7. 15 Figure 2-9 Switching state S8. 16 Figure 2-10 Algorithm for balancing Flying capacitor. 17 Figure 3-1: Carrier wave for CB-PWM case.
18 Figure 3-2 Flowchart of the 5L ANPC using CB PWM. 20 Figure 4-1 Space vectors of 5L-ANPC inverter. 23 Figure 4-2 Diving hexagon into 6 sectors. 27 Figure 4-3 Space vector in sector1.
28 Figure 4-4 Determine m1, m2 of Vref. 29 Figure 4-5 Switching sequence arranged in a symmetrical pattern. 33 Figure 4-6 Effect of redundant switching states on the FC voltages. 33 Figure 5-1 Space vector diagram for the 5L ANPC reducing CMV.
35 Figure 5-2 Switching voltage vector in Sector I to reduce CMV. 36 Figure 5-3 Switching sequence in region 5. 37 Figure 6-1 Model of 5L ANPC in MATLAB Simulink. 38 Figure 6-2 Vpp, Vpn, and I phase for CBPWM with m = 0.
39 Figure 6-3 Vpp, Vpn, and I phase for CBPWM with m = 0. 39 Figure 6-4 Vpp, Vpn, and I phase for CBPWM with m = 0. 40 vii Figure 6-5 Vpp, Vpn, and I phase for CBPWM with m = 0. 40 Figure 6-6 Common-mode voltage when m =0.8by using SinPWM.
41 Figure 6-7 THD I of SinPWM. 41 Figure 6-8 THD Vpn and Vpp of Sin PWM. 42 Figure 6-9 Vpp, Vpn, and I phase for SVPWM with m = 0. 42 Figure 6-10 Vpp, Vpn, and I phase for SVPWM with m = 0.
43 Figure 6-11 Vpp, Vpn, and I phase for SVPWM with m = 0. 43 Figure 6-12 Common-mode voltage when m = 0. 44 Figure 6-13 THD I of SVPWM. 44 Figure 6-14 THD Vpn and Vpp of Sin PWM.
45 Figure 7-1 Summary the losses in IGBT module. 46 Figure 7-2 Specification of RGW60TS65CHR. 48 Figure 7-3 The total losses of the ANPC when m = 0. 48 Figure 7-4 CMV voltage at m = 0.2 in CBPWM and SVPWM.
49 viii LIST OF TABLES Table 2-1: Single phase Switching states of 5L-ANPC Inverter. 5 Table 2-2 Switching state at S1. 7 Table 2-3 Switching state at S2. 8 Table 2-4: Switching state S3.
9 Table 2-5 Switching state S4. 11 Table 2-6: Switching state S5. 12 Table 2-7 Switching state S6. 13 Table 2-8 Switching state S7.
15 Table 2-9 Switching state S8. 16 Table 3-1 VXN and Switching states corresponding with Vref and Vcar. 18 Table 4-1 States and amplitude of space vector. 24 Table 4-2 Dividing sector.
28 Table 4-3 Subsector based on m1, m2. 30 Table 4-4 Duty cycles of each subsector. 32 Table 6-1 Simulation parameters for ANPC inverter.1 Background Multilevel topologies provide a clever way of connecting switches in series, thus enabling the processing of voltages that are higher than the device rating. The industry’s need for medium voltage drives has triggered considerable research in this field, in which most applications include drives for pumps, blowers, compressors, conveyors, ….
In general, multilevel converters are effective means of reducing harmonic distortion and dv/dt of the output voltages, which makes this technology applicable to utility interfaces and drives. There are a limited number of topologies that provide multilevel voltages and are suitable for medium-voltage applications. The most known topologies are the neutral-point-clamped (NPC), the flying capacitor (FC), cascade, … The NPC multilevel inverter shown in Figure l(a) is a natural extension of the three- level converter presented by Nabae (3L-NPC). After being introduced in 1981, NPC has widely used in industry, especially in medium-voltage applications.
The advantage of the NPC is its simple structure and low cost. However, the disadvantages are the unbalance of the DC voltage, and the differences of the diode voltage ratio. The benefit while using FC is the ability to balance the capacitor voltage. But it is quite hard to carry and priceful due to its bulky size and expensive components.
Figure 1(c) describes a cascade inverter. This structure, on the one hand, will reduce the voltage stress on H-bridge switches and boost voltage. On the other hand, there are numerous of components, which will increase the size and complicate topology. 2 Figure 1-1:NPC inverter topology and FC inverter topology Based upon the previous description, the Active NPC (ANPC) multi-level converter combines the flexibility of the multi-level FC inverter with the robustness of industrial NPC converters to generate multilevel voltages.
The proposed concept called ANPC (5L-ANPC) converter was first proposed in 2005 by ABB to eliminate the disadvantages of the NPC and the FC topology. The next part is about the target of the thesis.2 Problem Definition In this dissertation, the author’s aims were to model and control the 5L-ANPC. The achieve this goal, there are several objectives shown below: - Study the NPC. - Study the 5L-ANPC.
- Study the carrier-based pulse width modulation (CBPWM). - Study the space vector pulse width modulation (SVPWM) to reduce/eliminate Common-Mode Voltage (CMV). - Modelling the ANPC with MATLAB Simulink - Simulation results through MATLAB and PLECS.3 Thesis agenda There are 8 main parts - Chapter 1: Introduction - Chapter 2: Overview of the 5L-ANPC - Chapter 3: CBPWM for 5L-ANPC - Chapter 4: SVPWM for 5L-ANPC - Chapter 5: Proposed SVPWM to reduce CMV - Chapter 6: Simulation results - Chapter 7: Loss calculation - Chapter 8: Conclusion and Future works 4 Chapter 2. Overview of the 5L-ANPC 2.1 The 5L-ANPC Topology The topology of the 5L-ANPC inverter is shown in Fig.
It includes 3 phase legs, each phase leg comprises four complementary switch pairs (Sw1x and Sw2x), (Sw3x and Sw4x), (Sw5x and Sw6x), (Sw7x and Sw8x), 1 flying capacitor (FC) and two DC-link capacitors. The neutral point (NP) voltage is rated at half of the DC-link voltage. The load could be a three- phase RL load. P Sw5A Sw5B Sw5C + Sw3A Sw3B Sw3C C1 - Sw6A Sw6B Sw6C Sw1A Sw1B Sw1C O + + + Ca - Cb - Cc - Sw2A Sw2B Sw2C Sw7A Sw7B Sw7C + Sw4A Sw4B Sw4C C2 - Sw8A Sw8B Sw8C N Figure 2-1: Structure of 5L-ANPC inverter It can be seen the higher number of switches; the more voltage ratings are created.
Depending on the current flow path and the status of the FCs, we can choose suitable switching states to balance the FC voltages.