NATIONAL UNIVERSITY HO CHI MINH CITY UNIVERSITY OF INFORMATION TECHNOLOGY FACULTY OF COMPUTER ENGINEERING HUYNH LE ANH BAO - 19521241 TRAN HUU CHAU- 19521279 GRADUATION THESIS IMPLEMENT RISC-V AND INTEGRATE WITH SECURITY BLOCK ON FPGA COMPUTER ENGINEERING ENGINEER THESIS ADVISOR NGUYEN MINH SON HO CHI MINH, 2023 ACKNOWLEDGEMENT I would like to express my deepest gratitude and appreciation to the following individuals and organizations who have contributed to the successful completion of my graduation thesis. First and foremost, I am immensely grateful to my thesis advisor, PhD. Nguyen Minh Son, for his unwavering guidance, expertise, and invaluable support throughout this research journey. The insightful feedback, constructive criticism, and dedication have been instrumental in shaping the outcome of this thesis.
I would like to extend my sincere appreciation to the members of the thesis evaluation committee, The thesis evaluation committees, for their time, expertise, and valuable input. Their thorough evaluation and constructive comments have significantly enriched the quality of this thesis. My heartfelt thanks go to my family and friends for their unwavering support, encouragement, and understanding throughout this challenging endeavor. Their constant belief in me has been a source of motivation and strength during moments of self-doubt.
Once again, I extend my sincere appreciation to all those who have contributed to the realization of this graduation thesis. Their support and contributions have been invaluable, and I am truly grateful for their presence in my academic journey. Ho Chi Minh, 2023 Student researcher Huynh Le Anh Bao Tran Huu Chau CONTENTS CHAPTER 1. Processor archif€CfUT€.
Overview of the DTOC€SSOT. Comparison of CISC and RISC. Advanced Encryption Standard (AES). AES encryption and decryption process — 28.
RISC-V PROCESSOR DESIGN. Overview of processor đ€SiET. Functional blocks in the DFOC€SSOT. Instruction Memory bÌOCĂ.
Program Counter blOCK. Control Unit blOcK. Register File bÏOCK. -- ¿5S St k2 HH H00 0 uy 28 2.
Register File Floating-Point bÌOCK. Sign Extend DIOCK. àccc tt tre 33 2. Data Memory Processing BÌloCK.
Forwarding Unit block. DESIGN SYSTEM STRUCTURE. Overview about the protocol. Detailed signals of AXI Protocol in the thesis.
Visual simulation of write and read channel. Implementation of the advanced encryption standard (AES). An Overview of the Hardware Structure of AES-128. Packaging of AES-128 with AXI4 protocol.
Overview of designing archit€CtUTE.ccece ese eescseseseseeeescsessesesescseseeeseseessesneseseseeseees 46 3. Design on ViVAdO. Ips of Xilinx used in Block design. Memory Interface Generator IP (MIG 7 Series).
Central Direct Memory Access IP (CDMA). AXI Bram Controller P. SIMULATION AND DESIGN REVIEW. Test scenario ImOdel.-- ¿+ + St *SE*kEkề E112 211 rrrrườ51 4.
Summary results of implementation and design evaluation. Summary result of implementation of the RISC-V processor without the D extension. Summary result of implementation of the RISC-V processor with the D extension. Summary result of implementation of the AES-128.
Summary result of implementation of block design. TH HH gu 82 CHAPTER 5. CONCLUSION AND DEVELOPMENT. Accumulated eXP€Ti€TC€S.
Remaining proble1ms.- 5 + 1t TT HT ngư85 LIST OF FIGURES Figure 1.1: Google Pixel 6 SmartphOne.1: Execution stages in a DFOC€SSOT. ¿6 ¿St SE SEvskekrkrkrkrrrrrree 24 Figure 2.3: Program Counter BloCK.4: Control Unit ĐÏOCK. + - 5+ + xSk*v*‡EEk+kekEkEkreErrekekrkekrkrkrrrree 27 Figure 2.5: Register File bÏOCK.6: Register File Floating-Point bÌoCK.8: Sign Extend bÌOCĂ.c¿- 5c St SH 11121 1101011101001 10110 ri.11: Data Memory bÌOCĂ.--- - - ¿+5 ++5+s+c++++e+xexererexseexeeereex-ee DD Figure 2.12: Forwarding Unit block. ---¿-¿-«5¿+5+5++++++xese+zxexsevsex+ 36 Figure 3.2: General architecture of the AXI4 protocol.3: A read transaction of the prOtOCOl.----- +-+5+5++<+c+sec++x+x+evsse+ 40 Figure 3.4: A write transaction of the protocol.
cesses + ++x+xexexervrkekerrrre 40 Figure 3.5: Simulate read channels AXI4 of prOC€SSO.6: Simulate write channels AXI4 of pTOC€SSOT.8: AES-128 after packaging.9: System arChif€CfUTC.10: System design on ViVadO.--- cc: sec tt 47 Figure 3.11: Memory Interface Generator ÍP.13: Bram Controller and Block Memory Generator ÏP.- - -- 6 tt 3 BE ng HH gi49 Figure 3.15: System Cache ÏP. ¿+ + +12EEx kề H112 111 TH HH hư50 Figure 4.1: Test scenario I1Oel.--¿- - - ¿56+ £‡E+E‡E‡kEk#EEEEkkEErkrrkrkrkereree 51 Figure 4.2: Request from CPU through Read Address Channel.3: Receive data through Read Channel.4: CPU receives data from AXI4 BŨS.5: Executing process in CPU (1).6: Write data on AXI4 BUS. es esceseseseeseesesesesseseseessneneseseeeenenes 57 Figure 4.7: Executing process in CPU (2).--¿-¿ ¿5c + St +‡Evstekerrrrrerree 58 Figure 4.8: Executing process in CPU (3).9: Executing process in CPU (A).10: : Executing process in CPU (5).11 : Integer Regfile after finishing the loop in SUB1.12: Data memory after finishing the loop in SUB1 .13: Floating point Regfile after finishing SUB2.14: Data memory after finishing SUB2.16: The data of AES COFE. - -- 5c 5 SE E2 2 EEk2EErrrgrrey 68 Figure 4.17: The progress inside AES Core.
¿St srkeekeererrerred 68 Figure 4.18: The encode result of the online tOOl.19: Compare results of the simulation and the online tool.20: The data of cipher_text_in in the AES register file.21: The data of plain_text_out in integer register file .22: The result of online software †OOÌ.23: Comparison of online tool and simulation result .24: The used resource of RISC-V processor at 150Mhz.25: Used resource of blocks in RISC-V prOCeSSOT.26: The clock rate of RISC-V processor .27: Timing analysis for RISC-V processol.28: Consumption of power of the RISC-V processor.29: The used resource of blocks in RISC-V processor with the D extension —.30: The used resources in RISC-V processor with the D extension.31: The clock rate of RISC-V processor with the D extension.32: Timing analysis of RISC-V processor with the D extension .33: Power consumption of RISC-V processor with the D extension.34: The used resources of AES-128 .35 :The resources of blocks in AES-128.-- - 5-5 S+cc+c+crercee 78 Figure 4.36 : AES CÏOCK TaẲ€.- Sàn HH 78 Figure 4.37 : Timing analysis for AES-128. 55c 5+5 Sc+c+rerererirrrererrrree 78 Figure 4.38 : Consumption of power of the AES-128.39 : The clocks used in the block design Figure 4.40 : Timing analysis for the block design.41 : The used resource of the block design .42 : The used resource of IP in the block design.43 : Consumption of power of the block design. eects 81 LIST OF TABLES Table 1. 6 Sàn HH HH hư 11 Table 1.
cece 6-6 5S cescsesesseecscseseeseseesssessseseneneaee 13 Table 1.c cece eeeeseseseeesesessessesesesesseseseesensneseseseeanes 14 Table 1.---- ¿5525522 StS*2E2E£ESEeEkkekerrkrkrkereree 14 Table 1.5: U-format 1nStTUC(IOT. -- + <5 SE E2*E*E*E‡EEE*kEkEEEEEEEkk ghê 14 Table 1.6: RV32ID instruction Set.2: Program Counter block’s signnaÌ. - -- ¿5-5 5+ sv+x+eexvxererxexsrrrrx 26 Table 2.3: Control Unit block’s sig1naÌs.- - ¿6-5 S‡ESk+k‡EEEekerkrkekerrrek 28 Table 2.4: Register File block’s signnaÏÌS.--- - + ¿5-5 S2 £St+x+EeEekerrkrkererre 29 Table 2.5: Register Floating-Point block’s signnaÏs.-- - - 5+ 5sc++x+cscvser+ 30 Table 2.6: Signals of the Comparator DÏOCK.7: Signals of the Sign Extend block.8: Signals of the ALU bloek.----- --s-+-++c+c+sececzxsesceeeeecec-ee 2Ö Table 2.9: Convention of ALU_OP bit code.10: Signals of the FPU DIOCK.----¿¿-+5¿55+5++++s+xese+zxexseexee+ 35 Table 2.11: Signals of the Data Memory Processing block.12: Forwarding Unit block’s signal.1: Signals in AXI4 bus.-- 5c + SE SE k2 E1 1111 1111010121 111010101 gu. ¿s5 ++t + *tE+t+vE+EeeeEetxrxeerrsrrxeerrrrrrrrrsxrr 56 Table 6:10 10006.4: Finding 2 numbers GCD in Assembly.
5+ xxx 3E ng ngư 61 Table 4. - -- - + S+ +3 *Evt+eE+Erveexetrrxerrrrrrxeerrrrsrrrrsrer 62 Table 4.8: Performing (+-*/) floating point numbers in Assembly.9: Comparing division results between IEEE754 caculator and Risc-V core Table 4.10: Comparing table of the thesis course with other works. 82 LIST OF ABBREVIATIONS Abbreviation Full form IP Intellectual Property AXI Advanced eXtensible Interface Complex Instruction Set CISC Computer Reduced Instruction Set RISC Computer ARM Advanced RISC Machines RAM Random Access Memory CPU Central Processing Unit FBGA Field Programmable Gate Array ALU Arithmetic Logic Unit RTL Register Transfer Level AES Advanced Encryption Standard GRADUATION THESIS COMPUTER ENGINEERING ABSTRACT The thesis topic consists of three main contents revolving around the research on designing a RISC-V processor and packaging the processor into an IP following the AXI4 protocol. The first content aims to investigate the design of a RISC-V processor with D extension.
The processor comprises one ALU block for processing integer-related instructions (signed and unsigned) and a FPU block for calculating floating point numbers. The second content of the thesis focuses on packaging the processor. Most IPs in the Vivado software communicate with each other through the AXI4 or AXI3 bus. In this thesis, the RISC-V processor will be packaged according to the AXI protocol.
Subsequently, the RISC-V processor will be connected to other IPs in the Vivado Block Design, establishing the interconnection between the two contents. In the Block Design, RISC-V processor plays the role of a Master, requesting data reads from Slaves through the AXI4 bus, performing computations, and storing the results in the SDRAM. Additionally, it can send the results back to Slaves. The third content of the thesis focuses on implementing System Cache IP, which will help reduce the execution time, and Advanced Encryption Standard (AES), which will help encrypt the data.
The system will be implemented on Vivado 2021.2, use Verilog HDL, on Virtex-7 board, operate at 150MHz without the D extension and operate at 50MHz with the D extension. GRADUATION THESIS COMPUTER ENGINEERING OPENING The year 2021 has witnessed significant advancements in the field of the Internet of Things (loT), where connected devices have become pervasive in our daily lives. Simultaneously, the adoption of the RISC-V instruction set architecture (ISA) has gained momentum, revolutionizing the hardware landscape with its open- source nature. However, amidst this rapid expansion and innovation, the crucial aspect of hardware security in loT deployments has come into focus.
As IoT continues to grow and interconnect billions of devices, concerns about privacy, data integrity, and security vulnerabilities have escalated. The diverse range of interconnected devices, often with limited resources and varying security measures, poses challenges for ensuring robust hardware security. Threats such as unauthorized access, data breaches, device tampering, and malicious attacks present real risks that demand comprehensive security solutions. In parallel, the emergence of the RISC-V ISA as an alternative to proprietary architectures has introduced both opportunities and challenges in terms of hardware security.
While RISC-V's open nature encourages innovation, customization, and transparency, it also requires careful consideration of security measures to address potential vulnerabilities. The group proposes to design the integrated security system on the Vivado software toolset version 2021.2 from Xilinx, using the Virtex-7 board. The desired operating frequency of the system is 100MHz and the results can be displayed in the shortest possible time (100MHz). The thesis focuses on three main objectives.
The first objective is to design a RISC-V processor with an extension for double floating point, aiming to increase the number of instructions that can be processed in the processor pipeline. The second objective is to try implement AES-128 for encrypting. The third objective is to refine the RISC-V processor into a Master capable of communicating with other Slaves through the AX14 bus. GRADUATION THESIS COMPUTER ENGINEERING CHAPTER 1.
Overview of the processor With the advent of remarkable technological advancements, processors have emerged and undergone rapid development over time. Prominent chip manufacturers, such as Intel, Apple, AMD, Qualcomm, MediaTek, and others, have introduced their own branded processors that have gained widespread commercialization. A processor, also known as a central processing unit (CPU), is an electronic computer component constructed using ultra-small transistors integrated onto a compact area. While the CPU is the most well-known processor component, various other components in a computer also possess their own processors.
For instance, graphics cards feature dedicated processors. Prior to the introduction of processors, CPUs were built using separate small-scale integrated circuits, each containing approximately a dozen transistors. The first processing chips emerged in the early 1970s and were primarily utilized for electronic computing or algorithms involving binary-coded decimal (BCD) numbers. Subsequently, 4-bit and 8-bit processors were introduced.
One of the most significant advancements was the introduction of the MC68000 (68K) chip in 1979, which offered a large memory space, high speed, and reasonable cost, becoming an iconic CPU design. The BELLMAC-32A chip from AT&T Bell was the world's first 32-bit processor featuring a complete 32-bit data path, bus structure, and 32-bit address.