MINISTRY OF EDUCATION AND TRAINING HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION GRADUATION THESIS MAJOR: COMPUTER ENGINEERING TECHNOLOGY INTEGRATING THE SUPERSCALAR ARCHITECTURE INTO A 32-BIT RISC-V CPU INSTRUCTOR: TRUONG NGOC SON STUDENT: PHAM QUANG MINH Ho Chi Minh city, June 2024 HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION FACULTY FOR INTERNATIONAL EDUCATION GRADUATION PROJECT INTEGRATING THE SUPERSCALAR ARCHITECTURE INTO A 32-BIT RISC-V CPU PHẠM QUANG MINH Student ID: 20119181 Major: COMPUTER ENGINEERING Ho Chi Minh City, June 2024 1 HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION FACULTY FOR INTERNATIONAL EDUCATION GRADUATION PROJECT INTEGRATING THE SUPERSCALAR ARCHITECTURE INTO A 32-BIT RISC-V CPU PHẠM QUANG MINH Student ID: 20119181 Major: COMPUTER ENGINEERING Advisor: TRƯƠNG NGỌC SƠN, Assoc. Ho Chi Minh City, June 2024 2 3 4 THE SOCIALIST REPUBLIC OF VIETNAM Independence – Freedom– Happiness Ho Chi Minh City, July 02, 2024 PRE-DEFENSE EVALUATION SHEET Student name: Pham Quang Minh Student ID: 20119181 Major: Computer Engineering Technology Project title: Integrating the superscalar architecture into a 32-bit RISC-V CPU Name of Reviewer: Do Duy Tan, Ph. Content and workload of the project The content is appropriate for the topic of student’s thesis. Strengths: The thesis is well-organized and written.
Weaknesses: - Clearly explain the block diagrams in Chapter 3 - Clearly explain simulation results in Chapter 4 e., adding some marks/highlights in the figures. Approval for oral defense? (Approved or denied) Approved 5. Overall evaluation: (Excellent, Good, Fair, Poor) Good 6.5 (in words: Eight point five) Ho Chi Minh City, July 02, 2024 REVIEWER (Sign with full name) 5 THE SOCIALIST REPUBLIC OF VIETNAM Independence – Freedom– Happiness -------- EVALUATION SHEET OF DEFENSE COMMITTEE MEMBER Student name: Phạm Quang Minh Student ID: 2 0 1 1 9 1 8 1 Major: Computer Engineering Project title: Integrating the Superscalar architecture into a 32-bit RISC-V CPU Advisor: Trương Ngọc Sơn, Assoc. Name of Defense Committee Member:.
Content and workload of the project .) Ho Chi Minh City, month day, year COMMITTEE MEMBER (Sign with full name) 6 ACKNOWLEDGEMENTS First, I would like to express our sincere gratitude to the Faculty of International Education and the School Board of the Ho Chi Minh City University of Technology and Education for creating the ideal surroundings for me to pursue my project. Additionally, I would like to extend our sincere gratitude to the advisor, Assoc. Truong Ngoc Son consistently monitors the learning environment and supports and develops growth possibilities for every student generation. Last but not least, lack of expertise and slow implementation make it impossible for me to avoid blunders.
Your comments and ideas are appreciated as we work to make this topic better. Regards and many thanks for your assistance. Student PHẠM QUANG MINH 7 DISCLAIMER I hereby declare that the project "INTEGRATING SUPER ARCHITECTURE INTO RISC-V 32-BIT CPU" is my own research product, the simulations, and research results are accurate and done entirely under my supervision. Direction of lecturer, Associate Professor.
Truong Ngoc Son. The report also does not overlap with any other source. The document also includes a number of references that are meticulously cited and labeled. I take full responsibility for this commitment to the faculties, faculties, and schools.
Student PHẠM QUANG MINH 8 ABSTRACT The topic "Integrating the Superscalar microarchitecture into a 32-bit RISC-V CPU" includes 2 goals with the main goal being to integrate the Superscalar microarchitecture into a 32-bit RISC-V microprocessor and the secondary goal being to present a table data compares performance before and after integration to demonstrate effectiveness. To implement the project's goals one by one, the implementation team researched the development process of the Superscalar microarchitecture and learned about simpler previous versions, the Single Cycle microarchitecture and the Pipeline microarchitecture, and Realizing that the Superscalar microarchitecture was developed and inherited from the above two versions, the team decided to re-implement the entire development process including 3 microarchitectures: Single Cycle, Pipeline, and Superscalar. After completing the design and simulation, the team will provide a performance comparison table to complete the remaining goal of demonstrating the effectiveness of the Superscalar microarchitecture. The important part of the topic is the detailed design of each module block within the Single Cycle microarchitecture, the simplest version to show inheritance from which to develop the following versions based on that inheritance.
Pipeline and Superscalar. In addition, design verification is equally important and is based on the RISC-v architecture which will be detailed below. The research and development result of the implementation team is to produce waveforms from the ModelSim simulator and analysis to prove the design and test the design that has been completed by the team and to draw conclusions about the effectiveness when Integrate the Superscalar microarchitecture into a 32-bit RISC-V microprocessor based on the data table. This report presents the research and simulation design of a 32-bit RISC-V microprocessor with the first goal of integrating the Superscalar microarchitecture into the microprocessor and executing the RISC-V ISA specifically the RV32I subset.
The design process of 32-bit microprocessors with RISC-V architecture and Superscalar microarchitecture will be developed and inherited from 32-bit microprocessors with simpler microarchitectures such as Single Cycle and Pipeline. In addition to the goal of successfully integrating the microarchitecture, this article will provide a performance comparison table between the RISC-V processor with the Superscalar microarchitecture and other microarchitectures such as Single Cycle and Pipelines. The device can implement all the details manually through the Verilog hardware description language in the ModelSim simulator. 9 TABLE OF CONTENTS ACKNOWLEDGEMENTS.
9 TABLE OF CONTENTS. 10 LIST OF FIGURES. 12 LIST OF TABLES. 14 LIST OF ABBREVIATIONS.
RESEARCH GOAL AND LIMITATIONS. 17 CHAPTER 2: THEORETICAL BASIS OF RISC-V MICROPROCESSOR AND SUPERSCALAR MICROARCHITECTURE. RISC-V Instruction Set Architecture. THE COMPONENTS, BLOCKS INSIDE RISC ARCHITECTURE.
Registers in the RISC-V CPU. The memory in the RISC-V CPU. The main blocks of RISC-V CPU. RV32I INSTRUCTION SET ARCHITECTURE.
Reasons to choose RV32I instruction set. Instruction set inside the RV32I ISA. SUPERSCALAR MICROARCHITECTURE ON RISC-V CPU. Inheritance in Superscalar microarchitecture.
The Single Cycle microArchitecture on RISC CPU. The Pipeline microArchitecture on RISC CPU. The Superscalar microArchitecture on RISC CPU. 37 CHAPTER 3: DESIGN A 32-BIT RISC-V PROCESSOR WITH SUPERSCALAR MICROARCHITECTURE INTEGRATION.
EXECUTING PROCESS OF SUPERSCALAR ARCHITECTURE. Instruction execution process of Superscalar microarchitecture. Optimize the instruction execution process. INSTRUCTION FETCH (IF) PHASE.
INSTRUCTION DECODE (ID) PHASE. WRITE BACK (WB) PHASE. VERIFY RESULTS USING DATA MEMORY AND REGISTER MEMORY. THE PERFORMANCE COMPARISON.
Executing time of Single Cycle microarchitecture on RISC-V CPU. Executing time of Pipeline microarchitecture on RISC-V CPU. Executing time of Superscalar microarchitecture on RISC-V CPU. 62 CHAPTER 5: CONCLUSION AND FUTURE WORK.
67 11 LIST OF FIGURES Figure 1: RISC architecture diagram. Page: 12 Figure 2: RISC CPU block diagram. Page: 13 Figure 3: RISC-V base unprivileged integer register state [2]. Page: 17 Figure 4: The 32-bit RISC-V CPU processing stages.
Page: 18 Figure 5: Data Field [2]. Page: 20 Figure 6: Single Cycle and Pipeline microarchitecture. Page: 22 Figure 7: The Pipeline and Supermircoarchitecture. Page: 23 Figure 8: All the stages in the Single Cycle microarchitecture.
Page: 24 Figure 9: The Single Cycle Microarchitecture. Page: 25 Figure 10: All the stages in the Pipeline microarchitecture. Page: 26 Figure 11: Instruction processing in Pipeline microarchitecture. Page: 27 Figure 12: The Pipeline 5 stages microarchitecture.
Page: 28 Figure 13: All the stages in the Superscalar microarchitecture. Page: 29 Figure 14: Instruction executing process of 2 microarchitectures. Page: 30 Figure 15: Superscalar microarchitecture flowchart. Page: 31 Figure 16: The Superscalar microarchitecture.
Page: 32 Figure 17: Inside of the Instruction Decode phase. Page: 32 Figure 18: Instruction Fetch block diagram. Page: 35 Figure 19: Control Unit block 1, 2. Page: 36 Figure 20: Immediate Generator block 1, 2.
Page: 36 Figure 21: Register file block. Page: 37 Figure 22: Select Pipeline block. Page: 37 Figure 23: ID_EX pipeline register. Page: 38 Figure 24: The Execution block diagram.
Page: 39 Figure 25: EX_MEM pipeline register. page: 39 Figure 26: Data memory block. Page: 40 Figure 27: MEM_WB pipeline register. Page: 40 Figure 28: Write back Mux block.
Page: 41 Figure 29: Result interface. Page: 42 Figure 30: Instruction Fetch stage. Page: 44 12 Figure 31: ALU results. Page: 44 Figure 32: The waveform of the 10 implemented instructions.
Page: 47 Figure 33: The execution time of the 32 bit RISC-V Single Cycle processor. Page: 51 Figure 34: The execution time of the 32 bit RISC-V Pipeline processor. Page: 53 Figure 35: The execution time of the 32 bit RISC-V Superscalar processor. Page: 54 13 LIST OF TABLES Table 1: Instruction set format and their set type.
Page: 23 Table 2: The 10 implemented instructions. Page: 28 Table 3: 16 value assignment instructions. Page: 50 Table 4: The 10 implemented instructions with values. Page: 52 Table 5: Data memory.
Page: 53 Table 6: Register value. Page: 53 Table 7: Statistical table of clock value testing. Page: 57 Table 8: Statistical table of clock value testing. Page: 58 Table 9: Statistical table of clock value testing.
Page: 60 14 LIST OF ABBREVIATIONS Abbreviations Descriptions ALU Arithmetic logic unit CPU Central Processing Unit HDL Hardware Description Language IMEM Instruction Memory ISA Instruction Set Architecture RISC Reduced Instruction Set Computer REG Register 15 CHAPTER 1: INTRODUCTION 1. OVERALL Microprocessors and Microcontrollers are typically designed based on two main computer architectures: Complex Instruction Set Computer (CISC) and Reduced Instruction Set Computer (RISC). CISC emphasizes on diverse Instruction Set Architecture (ISA) with different instruction formats and addressing modes, requiring complex Control Units. In contrast, RISC processors have smaller instruction sets, fewer addressing modes, fixed instruction length, and load-store architecture, resulting in faster instruction execution and higher overall performance.
compared to CISC processors [1]. RISC-V instruction set architecture, known for its simplicity and modularity, provides a flexible platform to explore different execution models [1]. Some microarchitectures implementing the RISC-V instruction set will improve performance by overlapping the execution of different instruction stages, such as a 5-stage pipeline (Fetch, Decode, Execute, Memory Access,Rewrite) [2]. However, pipelined execution can be limited by data dependencies between instructions.
Superscalar processors address this limitation by combining multiple execution units, allowing parallel execution of independent instructions [2]. This approach has the potential to increase performance significantly, but it also introduces complexity in instruction planning and dependency handling. This study delves into the design and simulation of a RISC processor carrying a superscalar microarchitecture using the RISC-V instruction set, specifically the RV32I sub-instruction set. The main goal of the project is to integrate the Superscalar microarchitecture into a RISC processor, thereby providing data demonstrating the improvement in performance before and after integrating the microarchitecture using the Verilog hardware description language in ModelSim simulator.
The research in this topic will provide the team with in-depth understanding of the process of designing a RISC-V microprocessor with Superscalar microarchitecture. RESEARCH GOAL AND LIMITATIONS Research objective: The group's research project "Integrating Superscalar microarchitecture into 32-bit RISC-V CPU" includes 2 goals with the main goal being to integrate Superscalar microarchitecture into microprocessors 32-bit RISC-V and a secondary goal is to present a comparison table of operational data before and after integration to demonstrate performance improvements. Research limitations: The team's research topic "Integrating Superscalar microarchitecture into 32-bit RISC-V CPU" includes: + Regarding the RV32I sub-instruction set, the user group only uses 10 commands in the RV32I sub-instruction set instead of the entire sub-instruction set, specifically the commands add, sub, and, or, slt, addi, ori, andi, lw, sw to ensure the difficulty of the topic is commensurate with the group's ability.