MINISTRY OF EDUCATION AND TRAINING HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION GRADUATION THESIS MAJOR: COMPUTER ENGINEERING TECHNOLOGY ENHANCING EFFICIENCY OF TIME-DOMAIN WINNER-TAKE-ALL CIRCUIT STRUCTURE FOR NEUROMORPHIC APPLICATION INSTRUCTOR: TRUONG NGOC SON STUDENT: NGO TIEN TU Ho Chi Minh city, July 2024 HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION FACULTY OF INTERNATIONAL EDUCATION GRADUATION PROJECT ENHANCING EFFICIENCY OF TIME-DOMAIN WINNER-TAKE-ALL CIRCUIT STRUCTURE FOR NEUROMORPHIC APPLICATION NGO TIEN TU Student ID: 20119175 Major: COMPUTER ENGINEERING TECHNOLOGY Advisor: TRUONG NGOC SON, Assoc. PhD Ho Chi Minh City, July 2024 HO CHI MINH CITY UNIVERSITY OF TECHNOLOGY AND EDUCATION FACULTY OF INTERNATIONAL EDUCATION GRADUATION PROJECT ENHANCING EFFICIENCY OF TIME-DOMAIN WINNER-TAKE-ALL CIRCUIT STRUCTURE FOR NEUROMORPHIC APPLICATION NGO TIEN TU Student ID: 20119175 Major: COMPUTER ENGINEERING TECHNOLOGY Advisor: TRUONG NGOC SON, Assoc. PhD Ho Chi Minh City, July 2024 THE SOCIALIST REPUBLIC OF VIETNAM Independence – Freedom– Happiness -------- Ho Chi Minh City, July 5, 2024 GRADUATION PROJECT ASSIGNMENT Student name: Ngo Tien Tu Student ID: 20119175 Student name: __________________________ Student ID: ___________________ Student name: __________________________ Student ID: ___________________ Major: Computer Engineering Technology Class: 20119175 Advisor: Truong Ngoc Son, Assoc. PhD Phone number: (+84) 931 085 929 Date of assignment: _____________________ Date of submission: _____________ 1.
Project title: Enhancing Efficiency of Time-Domain Winner-Take-All Circuit Structure for Neuromorphic Application. Initial materials provided by the advisor: ___________________________________ 3. Content of the project: _________________________________________________ 4. Final product: ________________________________________________________ CHAIR OF THE PROGRAM ADVISOR (Sign with full name) (Sign with full name) THE SOCIALIST REPUBLIC OF VIETNAM Independence – Freedom– Happiness -------- Ho Chi Minh City, June 24, 2024 ADVISOR’S EVALUATION SHEET Student name: Ngo Tien Tu Student ID: 20119175 Student name:.
Major: Computer Engineering Technology Project title: Enhancing Efficiency of Time-Domain Winner-Take-All Circuit Structure for Neuromorphic Application. Content of the project:. Approval for oral defense? (Approved or denied) Approved for oral defense 5. Overall evaluation: (Excellent, Good, Fair, Poor) Good 6.) Ho Chi Minh City, month day, year ADVISOR (Sign with full name) Trương Ngọc Sơn 1 THE SOCIALIST REPUBLIC OF VIETNAM Independence – Freedom– Happiness -------- Ho Chi Minh City, July 04, 2024 PRE-DEFENSE EVALUATION SHEET Student name: Ngô Tiến Tú Student ID: 20119175.
Design of Winner-Takes-All Circuits for Neuromorphic System Name of Reviewer: Pham Van Khoa (PhD. Content and workload of the project The project proposes a solution for the Winner-Take-All (WTA) circuit in neuromorphic applications using memristors. Strengths: Its strength lies in analyzing the limitations of current WTA circuits and suggesting a new solution using a current mirror circuit. Weaknesses: However, the circuit analyses in the paper are not sufficiently convincing to the reader, especially concerning the multi-input NAND circuit and the Current Control Delay circuit.
It is recommended that the authors include additional references to strengthen the rationale behind these proposed solutions. Approval for oral defense? (Approved or denied) .) Ho Chi Minh City, July 04 2024 REVIEWER (Sign with full name) THE SOCIALIST REPUBLIC OF VIETNAM Independence – Freedom– Happiness -------- EVALUATION SHEET OF DEFENSE COMMITTEE MEMBER Student name: Ngo Tien Tu Student ID: 20119175 Student name:. Major: Computer Engineering Technology Project title: Enhancing Efficiency of Time-Domain Winner-Take-All Circuit Structure for Neuromorphic Application. Name of Defense Committee Member:.
Content and workload of the project .) Ho Chi Minh City, month day , year COMMITTEE MEMBER (Sign with full name) DISCLAIMER This thesis is submitted for the degree of Computer Engineer at Ho Chi Minh city University of Technology and Education. The ideas and findings in this thesis are mine alone. They do not reflect the views of any groups. The data and conclusions in this thesis are based on my own research.
They are meant for academic purposes only. I have tried to make sure all the information is correct, but any mistakes are my responsibility. All sources of data and information are properly cited. This thesis cannot be used for commercial purposes or copied without my permission.
Ho Chi Minh City, July 2024 STUDENT (Sign with full name) i ACKNOWLEDGEMENTS I want to express my deep thanks to Associate Professor Truong Ngoc Son for his guidance, support, and encouragement throughout my research. His knowledge and advice were very helpful in completing this project. Without his help, this work would not have been possible. I also want to thank my colleagues and friends for their assistance and support.
Their help and encouragement were very important to me during this journey. Special thanks to the administrative at Ho Chi Minh city University of Technology and Education and Faculty of International Education for their assistance throughout my research. Their help made many things easier for me. Moreover, I appreciate Dr.
Pham Van Khoa, the leader of the Faculty of International Education, for notifying me of the final deadline and motivating me to complete the essay ahead of schedule. Finally, I am very grateful to my family for their constant support and understanding. My parents always encouraged me to do my best. Thank you all for your incredible support and encouragement.
ii TABLE OF CONTENTS DISCLAIMER. ii LIST OF FIGURES. v LIST OF TABLES. ix CHAPTER 1 : INTRODUCTION.5 Object and Scope of the Study .1 Object of the study.2 Scope of the study.
3 CHAPTER 2 : LITERATURE REVIEW AND BACKGROUND .1 The Inception of the Winner-Take-All Circuit.2 Application of WTA Circuits .3 Artificial Neural Network.5 Introduction to Memristors .6 Analog Memristor and Binary Memristor .7 Memristor Crossbar and Neuromorphic System. 19 CHAPTER 3 : DESIGN OF A WINNER-TAKE-ALL CIRCUIT .1 Voltage/Current Control Delay Output .1 Analog Signal to Signal in Time-domain .2 Voltage Controlled Delay .3 Current Control Delay .4 NAND Gate for 10 Input Signals .3 Comparison with state-of-the-art works. 39 CHAPTER 4 : DESIGNING A MEMRISTOR-BASED NEUROMORPHIC SYSTEM FOR PATTERN MATCHING .1 Design a Neuromorphic System for pattern matching problem. 41 CHAPTER 5 : RESULT AND DISCUSSIONS .2 Result in other samples.
56 iv LIST OF FIGURES Figure 2.1 Winner-Take-All Working Principle .2 Example of Current Conveyor WTA circuit .3 Binary Tree WTA circuit .4 Time-Domain WTA circuit .5 Some application of WTA ciruit .6 An example of perceptron .7 One-hot Encoding .8 Comparation between output of WTA circuit and ANN .9 Comparation between matrix multiplication and XNOR-Popcount.10 Two types of symbols which usually used .11 Conceptual symmetries of resistor, capacitor, inductor, and memristor .12 Physical model and circuit model of a memristor .15 Comparing between AND gate and Binary Memristor .16 Comparison between Von Neumann architecture and Neuromorphic Architecture .1 Schematic of proposed analog to time-domain signal .2 An example nmos.3 Schematic of a designed VCD circuit.4 The design of VCD block in Cadence Virtuoso .5 Delay in output response for each corresponding input voltage signals .6 Schematic of a designed CCD circuit.7 The design of CCD block in Cadence Virtuoso.8 Delay in output response for each corresponding input current signals .9 Schematic of a designed delay cell.10 The design of the delay cell in Cadence Virtuoso .11 The different of CCD block with 1 delay cell and 2 delay cell.12 Schematic of NAND Gate with 2 inputs.13 The schematic of NAND 3 inputs.14 Detect winner block .15 Design and simulation of detect winner block with 3 inputs.16 Proposed NAND gate with 10 inputs.17 Schematic of proposed WTA circuit for 10 voltage inputs .18 Simulation of WTA for 10 voltage inputs .19 Schematic of proposed WTA circuit for 10 current inputs .20 Simulation of WTA for 10 current inputs .1 Block diagram of binary memristor crossbar with 64 channels and block of sensitive current.2 XNOR operation when comparing 2 sequences.3 The schematics of the binary memristor crossbar circuit and the winner-take-all circuit.4 Samples of MNIST dataset .5 Digitalize the input sample.6 Flatten image and convert it to voltage.1 Simulation of MNIST with label 2 .2 The stable status of detecting winner circuit.3 The next state if two inputs simultaneously come .4 CCD circuit with 2 delay cells.5 Relationship between number of delay cell and pattern matching rate .6 Output of the first sample in WTA circuit with 3 delay cells.7 Original samples and test samples .8 The comparison between output waveform of sample 7 of the data and the sample 7 of the test data. 51 vi LIST OF TABLES Table 2.1 Working of XNOR-Popcount in neural network.3 Truth table of AND gate with 2 inputs .4 Binary memristor working as AND gate.1 Truth table of NAND gate with 2 inputs.2 Truth table of NAND gate with 3 inputs .3 Compare this proposed WTA circuit with state-of-the art works.1 Truth table of XNOR gate. 42 vii ABBREVIATION Abbreviation Meaning WTA Winner-Take-All CMOS Complementary Metal Oxide Semiconductor CC Current Conveyor BT Binary Tree TD Time-Domain IoT Internet of Thing ANN Artificial Neural Network HRS High Resistance State LRS Low Resistance State AI Artificial Intelligence ML Machine Learning VCD Voltage Controlled Delay CCD Current Control Delay FoM Figure-of-Merit viii ABSTRACT By the advancements in information processing systems, WTA circuits play a key role in various cognitive functions and decision-making systems. Neuromorphic systems are inspired by the biological brain.
In this research, a binary memristor crossbars is design to examine the function of a proposed WTA circuit. A time-domain WTA circuit is proposed. By the simulation of Cadence Virtuoso on Samsung 130nm CMOS technology, the proposed circuit show that the precision is 99.3% and increase up to 99.75% when adding 1or 2 delay cells. The MNIST dataset is resized to 8x8 and normalize to binary pixel value is examined by binary memristor crossbar with proposed WTA layer.
The result shows that the recognize rate is 60%, increase to 80 and 100% with 1, 2 and 3 delay cells, respectively.………………………………………………… ix CHAPTER 1 : INTRODUCTION The first chapter provides a detailed introduction to this essay. It covers the overview, the research subject, the methods used, and the goals of the essay. It also explains the main purpose of a Winner-Take-All circuit and neuromorphic system. Additionally, this chapter outlines how the rest of the report is organized.1 Introduction By the advancements in information processing systems such as fuzzy logic control, artificial neural networks, neuromorphic technology, telecommunication circuits, etc.
It is worth noting that winner-take-all (WTA) unit plays a vital role in various cognitive functions and decision-making processes [1] [2]. Winner-Take-All circuits are used to determine the maximum out of the multiple (voltage or current) inputs. The WTA circuits offer a wide array of application, such as realizing neural networks, data classification/clustering approaches, and image processing algorithms in complementary metal oxide semiconductor (CMOS) technology. Neuromorphic systems are inspired by the human brain.
It mimics biological brain structure and functionality to perform some specific tasks. These systems use artificial neurons and synapses to process information in a way that like how our brains work. One key component of these systems is the memristor, a device that can "remember" the amount of electrical charge that has passed through it, even though isolating with electric source. Memristor was predicted mathematically by Leon O.
Chua in 1971 [3], which is the fourth basic electronic element. And it was experimentally found in 2008 [4]. From that device, many researchers have developed a crossbar architecture, which has the potential to replace old computer architectures. A memristor crossbar is a type of advanced technology used in computers.
It is made up of many memristor. It is arranged for many rows and column of memristors. This design helps store and process information more efficiently than traditional methods. Memristor crossbars are important because they can make computers faster and more energy efficient [5] [6].
Many researchers are being studied for use in future memory and computing devices. Nevertheless, while much research has been done on the WTA circuit, a deeper understanding of its structure, operating principles, and possible applications remains an area full of potential. Many researchers and engineers are interest to find a new way to improve the performance, accuracy and the stability of the WTA circuits in difference conditions.